[SI-LIST] Re: What will happen when short the SERDES IO to GND?
- From: liuluping 41830 <liuluping@xxxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>, liuluping 41830 <liuluping@xxxxxxxxxx>
- Date: Fri, 11 Jul 2008 09:01:10 +0800
Hi steve and Richard:
Thank you for your reply; The problem comes from a practical application
that the XAUI travel two line card and a backplane ;The transmit pair or
receive pair could be DC-biased due to bent pin, so AC coupling capacitors at
the transmit pairs is neccesary as well as the receive pairs,the tradeoff is
more vias thus worse eye diagram.
Thanks and Regards,
LIU Luping
As Steve says - it depends.
Many XAUI style output drivers use majority passive termination to positive
supply. By connecting the output nods to gnd you'll be bypassing the current
control stage and starve it.
Most nodes should survive with the (usually) 50 Ohms between rails for short
times. Most will meet the hot plug protection rules. Long times on smaller
feature sizes could permanently damage the die due to the high
electro-migration. Depends on the design/linewidths. ESD doesn't tend to catch
these events unless spikes at insertion/removal occur as well. But assumed you
meant a DC short.
"short" or "terminate"? - big difference naturally.
Short will likely kill the signals, risks damage over time, terminate will
likely give collapsed swing at best.
Regards,
Richard
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: 09 July 2008 21:43
To: liuluping 41830
Cc: si-list@xxxxxxxxxxxxx; wangyongjin@xxxxxxxxxx
Subject: [SI-LIST] Re: What will happen when short the SERDES IO to GND?
The answer depends on the specific driver design. If it is a CML driver
as is common, the pull-up will heat up more than usual. Whether that is
a problem or not depends on how the IC mfg sized the pull-up.
Steve.
liuluping 41830 wrote:
> Dear all :
>
> What will happen when short the working SERDES IO,e.g.XAUI, without AC
> capacitor to GND ?
> Will the ESD circuit working to prevent chip damaging?Are there any papers
> related to this problem?
>
> Thanks and Regards,
>
> LIU Luping
>
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