[SI-LIST] Re: What do you do when the manufacturer's model doesn't match the measurements?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Iain Waugh <iwaugh_pub@xxxxxxxxxxxxxxx>
- Date: Fri, 27 Aug 2010 07:51:36 -0700
Iain, if you can, you should derive your probe parasitics using a
fixture similar to your PCB in the region you are probing. Depending on
just what you've got for probes, the capacitance specs could be quite
optimistic. Be wary of the proximity of whatever is between your test
point and the probe head amplifier to any nearby metal.
Steve.
Iain Waugh wrote:
> Hi Steve,
>
> Thanks for the reply. You've confirmed what I thought (which is great).
>
> The simulation model did include the probe's stated capacitance - we placed a
> cap to GND in the model at the point where we were probing to match.
>
> I can get hold of a 7.5GHz probe - I'll give it a try as a double-check
> against the 1GHz probe bandwidth, but that will have to wait until Monday.
>
> Best regards,
>
> Iain Waugh
>
>
> On 27/08/2010, at 11:33 PM, steve weir wrote:
>
>
>> No, you should never make assumptions about correlation that you haven't
>> verified. For sanity check you should set-up probes in the simulation
>> that match the PCB, and then compare the results. Ideally the probes
>> you set-up will be located such that they are meaningful with respect to
>> what the die sees, which is what you really care about.
>>
>> There are many ways to go wrong in each the simulation and measurement.
>> In your case, I think your scope probe bandwidth is woefully
>> inadequate. For DDR2, 2GHz is about the absolute minimum floor I would
>> consider measuring and then with substantial adjustment for the limited
>> bandwidth. 5GHz scope plus probe bandwidth would be a lot preferable.
>> You need to really understand the parasitics in your probing.
>> Hopefully, you included that in your modeling. Finally, you want to be
>> sure that your scope measurements don't suffer DSP spongiform
>> encephalopathy.
>>
>> Steve.
>> Iain Waugh wrote:
>>
>>> Hi all, please can you advise!
>>>
>>> Our aim is to prove the vendors' IBIS models on a dev board so we can have
>>> confidence that simulations of our own 400MHz DDR2 design (using the same
>>> parts) will be accurate. We're simulating with Hyperlynx 8.0 and have
>>> taken the most up-to-date IBIS models from the vendors' websites.
>>>
>>> We've made a pretty good free-form schematic model of the dev board with
>>> the target CPU and memories (plus 'scope probe at the receiver's pin). The
>>> initial simulations were horrible with a massively non-monotonic rising
>>> edge crossing the Vil and Vih levels of the receiver twice. We used a 6GHz
>>> LeCroy 'scope with 1GHz probes to measure the actual dev board's signal
>>> integrity and the edges were clean.
>>>
>>> In my mind, that proves that I can't trust the model. The catch, however,
>>> is that the vendor then told us to put the simulation probes at the die
>>> instead of at the pin. We re-simulated and the non-monotonic edges went
>>> away - they actually looked like the measurement!
>>>
>>> Would you trust the results of a simulation when the measured case only
>>> correlates with a simulation having probes in a different place? Can we
>>> use the wrong (but matching) model to guide us to the best routing
>>> topology? I'm tempted to just use standard good SI practises and ignore
>>> the simulations.
>>>
>>> Best regards,
>>>
>>> Iain Waugh
>>>
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>> --
>> Steve Weir
>> IPBLOX, LLC
>> 150 N. Center St. #211
>> Reno, NV 89501
>> www.ipblox.com
>>
>> (775) 299-4236 Business
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>>
>>
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>
>
>
--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
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