[SI-LIST] Re: Waveform edge ringing
- From: Conrad Herse <conrad.herse@xxxxxxxxxxxxxxxxxx>
- To: wolfgang.maichen@xxxxxxxxxxxx
- Date: Tue, 23 Nov 2010 13:07:43 -0600
Hitesh,
I agree with Wolfgang that the device datasheet *should* have
fundamental information like setup/hold times. Generic setup and hold
time requirements for the PCI bus are also specified in the PCI spec.
One other thing to watch out for is the under/overshoot specs. Some
commercial devices are PCI compatible, but not PCI compliant, meaning
they don't meet all the PCI specs. I've encountered devices which don't
tolerate the PCI under/overshoot requirements stated in the PCI spec.
Conrad
wolfgang.maichen@xxxxxxxxxxxx wrote:
> Hitesh,
>
> VIH and VIL should indeed be specified in the datasheet. I'd be surprised
> if the device lacks such fundamental specifications. Maybe unless it is a
> well-defined logic family (e.g. LVTTL or CMOS) where the author assumes
> that these thresholds are known (but it would at least state which logic
> family it is).
>
> What I meant with my statement is that you typically strive to strobe in
> the center of the bit interval, i.e. put the clock edge(s) as far away from
> the transition points of the data waveform. If you really have no idea what
> setup and hold time for your part could be, then I'd assume maybe 25% of
> your bit interval, leaving a 50% eye opening. That would put equal
> requirement on clock and data timing accuracy (jitter). But that is a very
> (!) rough guess and most likely conservative. Since you already do
> simulations it will pay to dig down a bit to determine the true values.
>
> Just my 2 cents
>
> Wolfgang
>
>
>
>
>
>
>
> "Nijagunamurthy,
> Hithesh (GE
> Intelligent To
> Platforms)" <wolfgang.maichen@xxxxxxxxxxxx>
> <hithesh@xxxxxx> cc
> Sent by: <si-list@xxxxxxxxxxxxx>,
> si-list-bounce@fr <si-list-bounce@xxxxxxxxxxxxx>
> eelists.org Subject
> [SI-LIST] Re: Waveform edge ringing
>
> 11/23/2010 10:35
> AM
>
>
>
>
>
>
>
> Wolfgang,
> Thanks for the reply.
> I could not understand what you meant by "Data lines in general will have
> less of a problem with
> such waveforms unless the clock strobes it very close to the bit boundary
> (which isn't a good thing to do anyway)".
>
> Where can I find the hold time info for VIH and VIL? I quickly glanced thru
> datasheet. But did not find anything.
>
> -Hithesh
>
>
> -----Original Message-----
> From: wolfgang.maichen@xxxxxxxxxxxx [mailto:wolfgang.maichen@xxxxxxxxxxxx]
> Sent: Wed 11/24/2010 12:00 AM
> To: Nijagunamurthy, Hithesh (GE Intelligent Platforms)
> Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Waveform edge ringing
>
>
> Hithesh,
>
> first thing to note is that VIH and VIH are typically static thresholds.
> I.e. the receiver is guaranteed to see a high only if the input stays above
> VIH for sufficiently long time. For very short pulses going above VIH (or
> below VOL), and without knowing the bandwidth / reaction time of the
> receiver you do not know whether it already switched. Worst case for you
> would be that the initial spike just barely toggles the clock input, then
> when it drops and rises again (this time to full level) it could toggle it
> again - the result being double-clocking (clock sees two rising edges where
> there should only be one).
>
> Also consider that what you have is only a simulation - unless your models
> are pristine and hyper-accurate (a rare case) reality may look quite
> different - the spike being larger, the peak or dip being more (or less)
> extreme, and so on. But the waveform indicates a good potential for trouble
> on the clock pin. Data lines in general will have less of a problem with
> such waveforms unless the clock strobes it very close to the bit boundary
> (which isn't a good thing to do anyway). Of course any such ringing eats
> into your setup/hold margin.
>
> Wolfgang
>
>
>
>
>
>
>
> "Nijagunamurthy,
> Hithesh (GE
> Intelligent To
> Platforms)" <si-list@xxxxxxxxxxxxx>
> <hithesh@xxxxxx> cc
> Sent by:
> si-list-bounce@fr Subject
> eelists.org [SI-LIST] Waveform edge ringing
>
>
> 11/23/2010 02:53
> AM
>
>
>
>
>
>
> I am doing signal integrity simulation for PCI Address/Data bus signals
> going from an FPGA to a Power PC.
> The signals are daisy chained from the FPGA to 6 Power PCs. The daisy
> chain routing is 55 ohm impedance controlled.
>
> The waveform edge has some ringing at VIH on the rising edge and VIL at
> the falling edge. The ringing is only for one cycle(see pic).
> Can this be counted as a valid waveform.
> Let's say this is input to a clock buffer.
> The part where I am confused is(on the rising edge) the waveform goes
> above VIH, so now the output of the receiver IC should be High. Now if
> the edge goes 200mV below VIH after say 1ns, and comes back to Vcc, will
> the output of the receiver change?
> There is similar behavior at VIL.
>
> Now, let's say this is Addr or data line. Would the setup time would be
> violated?
>
> Image - http://www.imgplace.com/viewimg217/6307/69wave.jpg
>
> Thanks.
> -Hithesh
>
>
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