[SI-LIST] Re: Waveform edge ringing
- From: "Nijagunamurthy, Hithesh (GE Intelligent Platforms)" <hithesh@xxxxxx>
- To: <wolfgang.maichen@xxxxxxxxxxxx>
- Date: Wed, 24 Nov 2010 00:05:25 +0530
Wolfgang,
Thanks for the reply.
I could not understand what you meant by "Data lines in general will have less
of a problem with
such waveforms unless the clock strobes it very close to the bit boundary
(which isn't a good thing to do anyway)".
Where can I find the hold time info for VIH and VIL? I quickly glanced thru
datasheet. But did not find anything.
-Hithesh
-----Original Message-----
From: wolfgang.maichen@xxxxxxxxxxxx [mailto:wolfgang.maichen@xxxxxxxxxxxx]
Sent: Wed 11/24/2010 12:00 AM
To: Nijagunamurthy, Hithesh (GE Intelligent Platforms)
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Waveform edge ringing
Hithesh,
first thing to note is that VIH and VIH are typically static thresholds.
I.e. the receiver is guaranteed to see a high only if the input stays above
VIH for sufficiently long time. For very short pulses going above VIH (or
below VOL), and without knowing the bandwidth / reaction time of the
receiver you do not know whether it already switched. Worst case for you
would be that the initial spike just barely toggles the clock input, then
when it drops and rises again (this time to full level) it could toggle it
again - the result being double-clocking (clock sees two rising edges where
there should only be one).
Also consider that what you have is only a simulation - unless your models
are pristine and hyper-accurate (a rare case) reality may look quite
different - the spike being larger, the peak or dip being more (or less)
extreme, and so on. But the waveform indicates a good potential for trouble
on the clock pin. Data lines in general will have less of a problem with
such waveforms unless the clock strobes it very close to the bit boundary
(which isn't a good thing to do anyway). Of course any such ringing eats
into your setup/hold margin.
Wolfgang
"Nijagunamurthy,
Hithesh (GE
Intelligent To
Platforms)" <si-list@xxxxxxxxxxxxx>
<hithesh@xxxxxx> cc
Sent by:
si-list-bounce@fr Subject
eelists.org [SI-LIST] Waveform edge ringing
11/23/2010 02:53
AM
I am doing signal integrity simulation for PCI Address/Data bus signals
going from an FPGA to a Power PC.
The signals are daisy chained from the FPGA to 6 Power PCs. The daisy
chain routing is 55 ohm impedance controlled.
The waveform edge has some ringing at VIH on the rising edge and VIL at
the falling edge. The ringing is only for one cycle(see pic).
Can this be counted as a valid waveform.
Let's say this is input to a clock buffer.
The part where I am confused is(on the rising edge) the waveform goes
above VIH, so now the output of the receiver IC should be High. Now if
the edge goes 200mV below VIH after say 1ns, and comes back to Vcc, will
the output of the receiver change?
There is similar behavior at VIL.
Now, let's say this is Addr or data line. Would the setup time would be
violated?
Image - http://www.imgplace.com/viewimg217/6307/69wave.jpg
Thanks.
-Hithesh
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