[SI-LIST] Re: Via model

  • From: icer world <icermail@xxxxxxxxx>
  • To: Zaiyi Liao <zaiyi.liao@xxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 20 Nov 2009 02:08:12 -0800 (PST)

         In my opinion,It's not proper to use the via model of Hyperlynx to do 
simulation above 7GHz, because It's just a simple model, which could be just 
for simulation below 1GHz.
         
         You should model the via by 3D field solver such as HFSS or Hspice and 
do simulation by ADS or other high frequency softwares.
         Via can be equal to a capacitor in low frequency, but It's complex in 
high frequency which you should model it by field solver. Hope my point  will 
help you ! For more information mail to me. 
          





________________________________
From: Zaiyi Liao <zaiyi.liao@xxxxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Sent: Fri, November 20, 2009 4:59:40 PM
Subject: [SI-LIST] Via model

Hello all:
      Can you give me some knowledge of via model?

      Now I'm using Hyperlynx. Via model in hyperlynx is a short transmission 
line with two caps to GND on each side . The influnece of stub is exhibited in 
value of caps, the longer the stub is , the lager the caps

will be. I simulate the S21 of such via model(Spice description below) ,I find 
there will be a fluctuation in S21(-2dB in ~7GHz, -0.2dB at 14Ghz). I think 
it's unreasonable, what is your opinion? What's the wrong of this

model?

      I'd like you can talk something about how to establish via model and how 
to check if this model is reasonable. Thank you very mush!

BR//Zaiyi Liao

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.SUBCKT thru10_22_B00

*  Right Via
* Padstack: "thru10_22_B00"  Drill.0mils
* layers to connect (ports)
*** connection to layer "SIGNAL_1_B00"
+ L1_1
*** connection to layer "SIGNAL_14_B00"
+ L27_1

C000 L1_1                0        2.80981e-014
T052 L1_1      0 L27_1      0    Z0'.3369 TD=3.26191e-011
C052 L27_1                0        1.65302e-013

*  Left Via
* Padstack: "thru10_22_B00"  Drill.0mils
* layers to connect (ports)
*** connection to layer "SIGNAL_1_B00"
+ L1_2
*** connection to layer "SIGNAL_14_B00"
+ L27_2

C000 L1_2                0        2.80981e-014
T052 L1_2      0 L27_2      0    Z0'.3369 TD=3.26191e-011
C052 L27_2                0        1.65302e-013

.ENDS

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~










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