Hi All, I am using an Intel Xeon processor in my design. I have got the ibs model for the processor and separate distributed package model in H-Spice .rlc format. Is there a way to integrate this package model into the ibs model, so that postlayout check becomes seamless. Also I am using cadence Si tool which needs .DML models. Ultimately I need to get a .DML model consisting of both package info and device buffer info. Thanking in advance for your suggestions. *************************** Harjeet Singh Randhawa Wipro Technologies 8520408. Xtn 4113. www.wipro.com *************************** -- Attached file included as plaintext by Ecartis -- -- File: InterScan_Disclaimer.txt **************************Disclaimer************************************************** Information contained in this E-MAIL being proprietary to Wipro Limited is 'privileged' and 'confidential' and intended for use only by the individual or entity to which it is addressed. You are notified that any use, copying or dissemination of the information contained in the E-MAIL in any manner whatsoever is strictly prohibited. **************************************************************************************** ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu