My comments below, under your original questions, preceded with >>. Disclaimer: The content of this message is my personal opinion only and although I am an employee of Intel, the statements I make here in no way represent Intel's position on the issue, nor am I authorized to speak on behalf of Intel on this matter. Jeff Loyer -----Original Message----- From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Burford Sent: Monday, November 20, 2006 8:15 AM To: si-list@xxxxxxxxxxxxx Subject: [SI-LIST] Thick vs. thin diff. pairs Dear all,=20 I would like to ask opinions, on the merits and disadvantages of using wide or narrow microstrip lines. From where I am sitting it looks like narrow microstrip diff. pairs have it won hands down. =20 Thick lines: More area...which gives more dielectric loss as dielectric loss over takes skin effect losses at higher frequencies. >>My sims showed that you'll want wide traces to reduce loss. See my article at: http://www.pcdandm.com/pcdmag/mag/0605/0605pcdm_digital.pdf More S11 because any corner on the line will give a greater area and more capacitance. >>Not an issue at current frequencies, as others indicate. Thicker substrates to keep the impedance at the right value. >>Yep, and wider traces do this too. Unfortunately, thicker substrates give more crosstalk, too (assuming distance between traces is held constant). As thicker microstrip lines go round a bend, the inter-pair skew will be more than for two narrow lines. >>Depends on pitch, not width (though obviously, narrow lines will probably be at a tighter pitch); not a big issue for current speeds, and can be accomodated. There is also the possibility of increased EMI from thicker substrates (been reading antenna design books). >>I don't think this is an issue - I'm with Ritchey on this one; haven't seen a system fail EMI yet because of radiation from microstrip traces. =20 So please someone tell me why should we use thicker lines? And also please could someone tell me the trip ups of HDI (high density interconnect) such as how small can one realistically go with back plane and inter-chip routing? =20 Thanks Mark =20 =20 =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: =20 //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu