[SI-LIST] Re: Thick vs. thin diff. pairs
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: Mark_Burford@xxxxxxxxxxx
- Date: Sun, 26 Nov 2006 19:36:41 -0500
Mark,
The proof is very simple as long as we assume lossless or low-loss cases
(so ultimetely it is an approximation, but a decent one for many practical
scenarios).
The characteristic impedance is Zo=sqrt(L/C). The propagation delay
is tpd=sqrt(LC). The prop delay depends on the length and velocity
of wave, which is speed of light divided by sqrt(Er). From these two
expressions, C=tpd/Zo, independently of the cross section
dimensions.
Regarding wider traces giving more attenuation: for a matched trace,
the attenuation in dB is 4.35*(G(f)*Zo+R(f)/Zo), where G(f) is the
admittance due to dielectric loss. Furthermore, G(f)=w*C*tan_d.
So based on all of the above, the attenuation of a matched trace
due to dielectric losses does not depend on the trace width as long
as the impedance is kept constant. The source of the confusion
might be that for a wider trace (if we keep the dielectric height
the same so that we allow for a lower characteristic impedance), the
G(f) conductivity term increases (but not the attenuation).
Regards,
Istvan
Mark Burford wrote:
>Thanks, very interesting about the capacitances and characteristic
>impedances. I am wondering if this has a proof or is it a very good
>approximation of what happens?
>
>I have read a few times that wider traces give larger dielectric losses
>hence I ask.
>Mark
>
>-----Original Message-----
>From: Istvan Novak [mailto:istvan.novak@xxxxxxxxxxx]=20
>Sent: 26 November 2006 17:40
>To: Mark Burford
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Thick vs. thin diff. pairs
>
>Mark and All,
>
>Sorry for the late response, I was on the road...
>
>In general, I am with Scott about using thin lines. The resistive
>losses help to smooth out the transfer profile, which helps to
>reduce data dependent jitter.=20
>
>On the other hand, a narrower trace does not reduce the
>dielectric loss or attenuation due to dielectric loss. The
>dielectric loss term is the product of the radian frequency,
>capacitance and loss tangent. Since capacitance is constant
>for a given characteristic impedance in a given material,
>C stays the same even if we use narrower traces (because
>we need to make the dielectric layer proportionally thinner).=20
>
>The same goes to the extra capacitance represented by the
>corners; for a given material and characteristic impedance, it
>does not depend on the trace width.=20
>
>One parameter that carries significance is the trace separation.=20
>Here the scaling works such that wider traces have a proportionally
>bigger absolute separation to achieve the same coupling coefficient.=20
>At bends and turns this translates to bigger skew.
>
>Regarding microstrip versus stripline, I did see systems failing
>with microstrip routing, whereas just putting the same routing
>into stripline solved the problem. It depends on the size of
>board, number and length of traces, skew and matching
>conditions. A few short traces are usually not a concern.
>
>Regards,
>
>Istvan Novak
>SUN Microsystems
>
>
>Mark Burford wrote:
>
>
>
>>Dear all,=20
>>I would like to ask opinions, on the merits and disadvantages of using
>>wide or narrow microstrip lines.
>>
>>>From where I am sitting it looks like narrow microstrip diff. pairs
>>
>>
>have
>
>
>>it won hands down.
>>
>>=20
>>
>>Thick lines:
>>
>>More area...which gives more dielectric loss as dielectric loss over
>>takes skin effect losses at higher frequencies.
>>
>>More S11 because any corner on the line will give a greater area and
>>more capacitance.
>>
>>Thicker substrates to keep the impedance at the right value.
>>
>>As thicker microstrip lines go round a bend, the inter-pair skew will
>>
>>
>be
>
>
>>more than for two narrow lines.
>>
>>There is also the possibility of increased EMI from thicker substrates
>>(been reading antenna design books).
>>
>>=20
>>
>>So please someone tell me why should we use thicker lines? And also
>>please could someone tell me the trip ups of HDI (high density
>>interconnect) such as how small can one realistically go with back
>>
>>
>plane
>
>
>>and inter-chip routing?
>>
>>=20
>>
>>Thanks
>>
>>Mark
>>
>>
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