[SI-LIST] Re: Strange Gnd Clamp V-I curve when generating IBIS
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 17 Dec 2004 13:52:54 -0500
> ... However, there are some folks out there who may
> be interested in how the bus floats, i.e. what will the
> voltage on a bus be when all buffers are in the high impedance
> state. In this case even these small currents become important.
> Would you really trust that?
Under suitable conditions, yes!
If a bus is supposed to float a certain way, say because one of the devices
has weak pull-ups in it, then these "leakage" currents probably are in the
high uA to low mA range. I probably can depend on that, as much as I could
on a 5k pull-up resistor.
For many digital circuits, leakage in the nA range would be in the noise and
can't be counted on to consistently pull the bus a certain way. But it's
not inconceivable. You just need to know where and what all your current
paths are. Many analog folks are OK with currents in the pA's.
Muranyi makes a good point, as I was hinting at, that the model creator
shouldn't second-guess his customers by assuming they don't care about
such low currents.
With an IBIS model, zeroing the leakage currents or truncating the tables
between GND and VCC, sends a message to the model user that the device
is really this ideal or perfect. If anything, it might have been better to
load up the tables with the worst-case data sheet values (say, +10 uA in the
max column and -10 uA in the min column), even if the SPICE model behavior
is much smaller.
Regards,
Andy
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