[SI-LIST] Re: Skew and Jitter
- From: "Clewell, Craig" <cclewell@xxxxxxxxxxxxxx>
- To: "'scott@xxxxxxxxxxxxx'" <scott@xxxxxxxxxxxxx>
- Date: Tue, 1 Apr 2003 11:47:46 -0500
Scott,
Could you clarify something for me from your last e-mail....
You mentioned that you create IBIS files from SPICE files and that they
correlate well, but then mention that flaws become apparent from lossy line,
package, via and connector SPICE models. Are you saying that SPICE modeling
is not valid for these structures?
Also, could you be more specific on the severe flaws that you have found in
these types of models you mentioned and how they impede accurate system
simulations.
I am also interested in understanding how the finished IBIS file reveals
flaws in simulation tools?
I'm not trying to be a Richard Head here, but just trying to understand what
you are saying.
Best Regards,
Craig
-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Tuesday, April 01, 2003 11:11 AM
To: rhaller@xxxxxxxxxx
Cc: jeff.loyer@xxxxxxxxx; twesterh@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Skew and Jitter
All,
We've been in the business of creating IBIS models for many years, both
from Spice models and from measurements. It is absolutely necessary to
correctly time correlate VT tables, and we have been doing this at
Teraspeed (and the other places) for many years with great success. When
correctly created, eye pattern simulations of IBIS models will correlate
well with the original Spice. In fact, once IBIS models are created with
this type of care and accuracy (as required by the IBIS 4.0
specification) then other flaws in simulation tools and modeling become
glaring. Areas such as lossy line modeling, package modeling, via
modeling and connector modeling, are often severly flawed and become
true impediments to faithful and accurate system simulations.
As for the VT correlation issue, this was not specifically dealt with in
IBIS version 3.2. This deficiency in the IBIS 3.2 specification has been
resolved in the IBIS 4.0 specification as follows:
| The data in all of the waveform tables should be time
| correlated. In other words, the edge data in each of the
| tables (rising and falling) should be entered with respect
to
| a single point in time when the input stimulus is assumed to
| have initiated a logic transition. All waveform extractions
| should reference a common input stimulus time in order to
| provide a sufficiently accurate alignment of waveforms. The
| first line in each waveform table should be assumed to be
the
| reference point in time corresponding to a logic transition.
| For example, assume that some internal rising edge logic
| transition starts at time = 0. Then a rising edge
| voltage-time table might be created starting at time zero.
| The first several table entries might be some "lead-in" time
| caused by some undefined internal buffer delay before the
| voltage actually starts transitioning. The falling edge
| stimulus (for the purpose of setting reference time for the
| voltage-time table) should also start at time = 0. And, the
| falling edge voltage-time table would be created starting at
| time zero with a possibly different amount of "lead-in" time
| caused by a possibly different but corresponding falling
edge
| internal buffer delay. Any actual device differences in
| internal buffer delay time between rising and falling edges
| should appear as differing lead-in times between the rising
| and the falling waveforms in the tables just as any
| differences in actual device rise and fall times appear as
| differing voltage-time entries in the tables.
best regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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