[SI-LIST] Sizing of on-chip MOS transistor decoupling capacitor
- From: "Yiran Chen" <cyr_1976@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 16 Mar 2004 16:04:18 -0000
Hi, guys
I am trying to find the most suitable DECAP design for the future
Technology, for example, 70 nm and beyond. In those technology node,
the leakage current becomes one major consideration and call for the
new or suitbale design of Decap.
I don't understand one thing: some people claim that the ESR of
transistor capacitor is around 1/12 of a camparable logic
transistor. That means usually the length of transistor capacitor
could be longer than the minimal size. My question is:
How to choose the size of Decap? We could use longer channel length
to enlarge the capacitance of MOS transistor decap as well as
enlarge the width of it to reduce the ESR. So, it seems the larger
the width is, the bettwer the decap is. Am I right? If so, we will
design a very long width MOS transistor Decap. However, it does not
look like that in the real design.
Also, could we change the diffusion size in specific process? For
example, in TSMC process, could we intend to enlarge the overlap
between the gate and diffusion? I am not familiar with that so may
need some helps.
Many thanks.
Yiran
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