[SI-LIST] Senior SI engineer and internship position available in HP Storage Division

  • From: "Cheng, Chris" <chris.cheng@xxxxxx>
  • To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 4 Sep 2014 20:10:15 +0000

Hi there,
I am the hiring manager so please send me your resume directly.
The intern position is in Fremont CA while the Senior SI position can be in 
Fremont, CA, Colorado Spring, CO or Houston, TX
Overall, if you have experience in jitter analysis, communication theories, 
stochastic process or statistical analysis, we are very interested in talking 
to you. The job descriptions are below:

----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Senior signal integrity engineer at HP UDU division
As a Senior Signal Integrity Engineer in HP Storage Works Division, you will be 
responsible to help develop the next generate high end enterprise storage 
solutions including servers and high density enclosures.

KEY RESPONSIBILITIES
·         Assist in system level SI design for storage server and JBODs
·         Perform SI electrical verification tests on proto type system
·         Perform channel analysis, EM simulations and jitter analysis of high 
speed SerDes buses such as PCIe, SAS or FCAL

Required:
·         BS/EE with 5+ years experiences or MS/EE with 3+ years experiences; 
PhD with research areas relevant to job requirements
·         Knowledge system level signal integrity design
·         Experience with high speed sampling/real time oscilloscopes, network 
analyzers
·         Knowledge of HSPICE simulations , EM analysis tools such as Ansys or 
CST Microwave studio and Matlab
·         Knowledge of basic channel analysis methodology
 
Desired:
·         Experience with Allegro PCB design tool sets
·         Knowledge of jitter analysis, communication theories, stochastic 
process or statistical analysis
-         Knowledge of SerDes design blocks such as FIR, CTLE, DFE or CDR 
designs

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Graduate signal integrity internship at HP UDU division
As a graduate intern in HP Storage Works Division, you will be responsible to 
help develop the next generate high end enterprise storage solutions including 
servers and high density enclosures.

KEY RESPONSIBILITIES
.         Assist in system level SI design for storage server and JBODs
.         Perform SI electrical verification tests on proto type system
.         Perform channel analysis, EM simulations and jitter analysis of high 
speed SerDes buses such as PCIe, SAS or FCAL

Required:
.         PhD candidates with research areas relevant to job requirements
.         Knowledge system level signal integrity design
.         Experience with high speed sampling/real time oscilloscopes, network 
analyzers
.         Knowledge of HSPICE simulations, EM analysis tools such as Ansys or 
CST Microwave studio and Matlab
.         Knowledge of basic channel analysis methodology
 
Desired:
.         Knowledge of jitter analysis, communication theories, stochastic 
process or statistical analysis
-         Knowledge of SerDes design blocks such as FIR, CTLE, DFE or CDR 
designs


Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company
 
+1 510 344 4439/ Tel 
chris.cheng@xxxxxx / Email 
4209 Technology Dr
Fremont, CA 94538
USA
 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Cheng, Chris
Sent: Tuesday, March 26, 2013 4:27 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Graduate student summer intern opportunity in HP Storage 
division in Fremont , CA

I have a summer internship opening for a graduate school level student doing SI 
related researches. 
The job location will be at Fremont, CA and the duration will probably be 
between June to September but can be flexible.
Prefer skills : Knowledge of Matlab, VNA, TDR, HFSS, HSPICE or AMI modeling 
will be a plus Typical assignment : Channel modeling and analysis, lab testing 
and validation of high speed storage products Please send your resume directly 
to me.
Thanks in advanced,

Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company
 
+1 510 413 5977 / Tel
chris.cheng@xxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
 


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  • » [SI-LIST] Senior SI engineer and internship position available in HP Storage Division - Cheng, Chris