Hi All, The problem with ignoring the capacitance of the line and relying totally on the transmission line effects is that there will be different levels on the receiving end for differeing digital transmission patterns. If you are considering a signal that is always alternating, the levels may degrade but are still above and below Vih and VIL. If the data is coded such that there is always an alternating value, data transmission is acceptable under these conditions. There are three classes of digital transmission on any buss, address,data, and control. rarely can the address be coded and clock signal integrity may be compromised with the transmission line only approach. If parallel termination is used for the clock, there will be no reflection but the levels suffer and may be unacceptable. In most cases, I have found that a driver that is capable of enough DC current to drive a parallel termination is easily capable of driving a series termination without DC load under equivalent loading conditions. there are different considerations for source synchronous busses as well as busses that use a clock recovery system. Thanks Jim Freeman Bob Patel wrote: > Hi! Anders, Even if I take a transmission line > approach the total capacitance faced by the driver > will always be there i.e. even if the edge rates are > faster and the driver is weak then the rise & fall > time will not be maintained at the receiver and if the > C is too large then the driver may not be able to > drive it above Voh. SO, either way this lumped > capacitance approach has to be taken into account to > determine the drive needed. > Thanks for the input. > Bob > --- "Anders Ekholm (ERA)" > <Anders.Ekholm@xxxxxxxxxxxxxxx> wrote: > > At high speed (HF) this will probably get you a > > pesimistic result. > > If you trace is long enough compared to your edge > > rates the driver will not > > see the load right away since it will see a > > transmission line. > > > > think what would happen with your formula if you > > trace was very long > > like a 1000meter cable, it would give you a > > capacitive load you would not be able to drive. > > > > If you are using the result to select an ASIC driver > > or something like that, you will > > choose unnecessary strong drivers if you base your > > selection on total capacitance of you trace > > (as long as we are talking fast edges). > > > > You might need a transmission line approache rather > > than a lumped capacitive load approache. > > > > Regards /Anders Ekholm > > > > > > > -----Ursprungligt meddelande----- > > > Fr> ån: Bob Patel [SMTP:whizplayer@xxxxxxxxx] > > > Skickat: den 9 januari 2002 21:02 > > > Till: si_list > > > Ämne: [SI-LIST] Total load capacitance > > > > > > > > > Hi! If i am calculating the total load capacitance > > > faced by the driver, can i use this equation: > > > Ctotal = C(trace)+ C(via) +Cin(i/p cap. of load)+ > > > Cout(o/p cap of driver) > > > Now if I add 5% then can I safely assume that if > > the > > > I?O is designed to drive this load then on the > > real > > > board there should not be a problem fro the driver > > to > > > source or sink current. > > > Thanks in advance > > > Bob > > > > > > > > > __________________________________________________ > > > Do You Yahoo!? > > > Send FREE video emails in Yahoo! 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