[SI-LIST] Re: SSTL2 classI without RS and RT on short length

  • From: Scott McMorrow <scott@xxxxxxxxxxxxx>
  • To: esteban.bernard@xxxxxxxxxx
  • Date: Fri, 07 Apr 2006 09:29:15 -0400

Bernard

At 250 MHz, you must have a resistor to Vtt in order to maintain DC 
balance around Vref.  Otherwise your DC wander due to pattern run length 
will cause excessive timing and voltage margin loss

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

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Bernard Esteban wrote:
> Hi,
>
> I'm currently designing a board with fpga(U1) and a chip(U2) where IO 
> are in levels SSTL2. Both chip are BGA 1mm and 0.8mm.
> 8 IO one-way U1 to U2, and 8 one-way U2 to U1.
> So 16 lines point to point. Clock frequency is 250MHz in single data rate..
> The two chips are very close, less than 1/2 inch.
> I made schematics with Rs and Rt, but they takes a lot of place, even is 
> I use fpga integrated Rs.
> I think this could be possible to connect these 2 chips without RS and 
> RT, but I dont have a simulator for my PCB router, and so, to validate 
> this solution.
> I found some papers and discussions were RT is not used, other paper 
> were RS is not used.
>
> Did you try this idea or did you think this idea can works with good 
> reliability ??
>
> Regards,
>
> Bernard
>
>   
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