[SI-LIST] Re: SSTL2 / HSTL Input buffer
- From: Robert Kezer <Robert.Kezer@xxxxxxxxxxxxx>
- To: "'jj_srini@xxxxxxxxxxxxxxx'" <jj_srini@xxxxxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Wed, 12 Nov 2003 16:12:52 -0500
If I understand the question, you are letting the input to a HSTL or SSTL
buffer
float?
If this is the case, the output of the input buffer is undefined and subject
to
any noise coupled on the floating input. Unless there is an internal pullup
or
pull down, which I doubt. This can lead to oscillatory behavior due to
enviromental
noise.
The worst case is if the output of the input buffer settles in the middle of
logical
threshold of the down stream gates it connects to. For deep sub-micron
technologies
this can lead to pre-mature failure due to the high probability of hot
electrons being
generated and striking the silicon-insulator interface at the bottom of the
poly gate.
Bob
-----Original Message-----
From: Srinivasan JJ (ASIC) - CTD, Chennai.
[mailto:jj_srini@xxxxxxxxxxxxxxx]
Sent: Wednesday, November 12, 2003 3:56 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SSTL2 / HSTL Input buffer
Importance: High
Hi
When not driven by any driver on a star topology of an SSTL2 or HSTL signal,
what would be the state of the output of input buffers which essentially
compares the signal level to a Vref and during such conditions, the signal
level is expected to be at mid level of Vtt = Vref.
Request immediate help....
Thanks in advance..
Warm Regards
J Srinivasan
Maya is the beauty of existent and non-existent co-existing...
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