[SI-LIST] Re: SSTL Standard
- From: Ray Anderson <reanderson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 21 Jul 2004 07:32:37 -0700
Ritika-
(I am assuming you are referring to SSTL_2 logic. I haven't reviewed the
spec documents for the other voltage families lately)
If you look at the JEDEC JESD8-9B document you will see that it says the
following with respect to Vdd:
> NOTE 1 There is no specific device VDD supply voltage requirement for
> SSTL_2 compliance. However
> under all conditions VDDQ must be less than or equal to VDD.
Furthermore the spec states that Vddq is specified at: 2.3 v min. and
2.7 v max.
From those bits of info one can infer that Vdd max is 2.7 volts .
(Vdd powers all associated circuitry except for the output buffers which
are powered by Vddq)
At least that is how I interpret the spec. Perhaps others who are more
familiar with the spec can elaborate on the topic.
-Ray Anderson
Ritika DUA wrote:
>Hi all,
>
>I Have a doubt regarding the Device Supply Voltage defined in the SSTL
>Standard.
>
>For what part of Ckt. will use this supply, and why the minimum value of
>this supply volatge should be equal to the Output Supply Voltage and
>max. can be anything.
>
>Any enlightment will be welcome.
>
>Regards
>
>Ritika Dua
>
.
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