[SI-LIST] SI Special Session in IEEE EMC 2012 International Symposium

  • From: "Ye, Chunfei" <chunfei.ye@xxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 31 Jul 2012 18:46:03 +0000

Dear all,

We have an exciting signal integrity special session on August 7, Tuesday, in 
2012 IEEE EMC International Symposium in Pittsburgh, Pennsylvania. It is 
chaired by Dr. Jianmin Zhang (Cisco) and myself (Chunfei Ye, Intel).  There are 
six excellent presentations from industry and academia. Please see below for 
papers and presenters. For more information on the papers and the symposium 
please visit http://www.emc2012.org

====================================================================================
TC10 Special Session: Channel Characterization and Modeling for High-Speed 
Signaling
Room 301/302, 1:30 PM - 5:30 PM, August 7, Tuesday
Chairs: Jianmin Zhang, Cisco Systems, Inc. and Chunfei Ye, Intel Co.
====================================================================================

1:30 PM: System Level Jitter Characterization of High Speed I/O Systems
Kyung Suk (Dan) Oh, Signal and Power Integrity, Rambus Inc., Sunnyvale, CA 

About the presenter: Dr. Dan Oh is currently responsible for driving the 
overall Si/Pi technical direction at Altera as well as leading the IC Product 
Development SI/PI team. Dan was most recently a Technical Director at Rambus 
Inc. where he defined the signaling roadmap, supported system definition of new 
product proposals, and drove IP development for innovative signaling solutions. 
He has over 20 years experience in the area of signal and power integrity. Dan 
received his Ph.D. in Electrical Engineering from the University of Illinois at 
Urbana-Champaign. He has numerous patents and papers in the areas of high-speed 
I/O modeling, simulation, and design. He is the lead author of the book 
"High-speed Signaling: Jitter Modeling Analysis, and Budgeting," and also 
serves on the technical program committees of leading conferences such as IEEE 
EPEPS, IEEE ECTC, and DesignCon.

2:00 PM: SI and PI Analyses of Complex IC Packaging Using Non-conformal Domain 
Decomposition Methods
Yang Shao, Zhen Peng, and Jin-Fa Lee, Department of Electrical and Computer 
Engineering, The Ohio State University, Columbus, OH 

About the presenter: Dr. Yang Shao is a Post Doctor Researcher at the 
ElectroScience Lab, the Ohio State University. She received her Ph.D. degree in 
Electrical Engineering from the Chinese Academy of Sciences in 2008. Her 
research interests are in scientific computing on the advancement of 
computational electromagnetics and multiphysics analysis. She is also 
interested in signal integrity and power integrity modeling, simulation and 
design of complex IC problems.

2:30 PM: A Measurement Based Methodology to Evaluate Die to Die Link 
Performance for High-speed IOs
Chunfei Ye*, Kai Xiao, Michael K Johnston, Ricardo U Chavez Cuadras, and 
Xiaoning Ye, *Intel Co., DuPont, WA

About the presenter: Dr. Chunfei Ye is Intel server group signal integrity 
technical lead responsible for USB/SATA/SAS and PCH/SOC package design. He 
obtained Bachelor Degree of Science in Mathematics in 1982 from Hangzhou 
University, China, and Ph.D. degree in Electrical and Electronics Engineering 
in 1994 from Southeast University, China. Before joining Intel in 2002, he 
worked with Shanghai Tiedao University, China, Massachusetts Institute of 
Technology, USA, and Institute of High Performance Computing, Singapore.

3:00 PM: A Fast and Accurate O(1) Solution to the Low-Frequency Breakdown 
Problem of Fullwave Solvers
Jianfang Zhu and Dan Jiao*, *School of Electrical and Computer Engineering, 
Purdue University, West Lafayette, IN

About the presenter: Prof. Dan Jiao  received the Ph.D. degree in electrical 
engineering from the University of Illinois at Urbana-Champaign, Urbana, in 
2001. She was with the Technology Computer-Aided Design (CAD) Division, Intel 
Corporation, until September 2005, as a Senior CAD Engineer, Staff Engineer, 
and a Senior Staff Engineer. She joined Purdue University, West Lafayette, IN, 
in September 2005, as an Assistant Professor with the School  of Electrical and 
Computer Engineering, where she is currently a tenured Associate Professor. She 
has authored two book chapters and over 160 papers in refereed journals and 
international conference proceedings. Her current research interests include 
computational electromagnetics, high-frequency digital, analog, mixed-signal, 
and RF integrated circuit design and analysis, signal and power integrity. More 
information about her can be found from https://engineering.purdue.edu/~djiao.

3:30 PM Break

4:00 PM: Differential Far-End Crosstalk Cancellation - Implementations and 
Challenges
Xiaoning Ye*, Kai Xiao, Raul Enriquez, *Intel Corporation, Hillsboro, OR

About the presenter:  Dr. Xiaoning Ye joined Intel in 2001. He is currently a 
technical lead in Platform Engineering Group (PEG) within Datacenter and 
Connected Systems Group (DCSG) working on signal integrity of high speed 
differential interconnects in Intel Server systems. Xiaoning Ye received his 
Bachelor and Master Degrees in electronics engineering from Tsinghua 
University, Beijing, China, in 1995 and 1997 respectively, and Ph.D. degree in 
electrical engineering from University of Missouri - Rolla (currently Missouri 
University of Science and Technology) in 2000. He has published over 30 IEEE 
papers, and holds 5 patents and 2 patent applications.

4:30 PM: ASIC Package Design Optimization for 10 Gbps and Above Backplane 
SerDes Links
Jane Lim*, Kai Soon Chow, Ji Zhang, Jianmin Zhang, Kelvin Qiu, Rick Brooks, 
*Cisco Systems, Inc., San Jose, CA

About the presenter:  Dr. Jane (Hong T) Lim is a senior manager at Cisco 
Systems, working on signal integrity of high-end networking products. She leads 
a SI team on high performance ASIC/board designs, high-speed signaling 
definition,  and interconnect technology enhancement. Prior to joining Cisco, 
she worked for LSI Logic on advanced packaging design and characterization.  
She specializes in ASIC/package/board SI/PI analyses, high bandwidth 
interconnect modeling,  and 10G/40G/100G Ethernet SerDes electrical 
requirements. Dr. Lim received her Ph.D. and MPhil degrees in Electrical 
Engineering from University of Cambridge, U.K.
=========================================================================

Regards

Chunfei Ye
Tel: 1-253-3712973
Enterprise Platform Signal Integrity
Intel Co.


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List forum  is accessible at:
               http://tech.groups.yahoo.com/group/si-list

List archives are viewable at:     
                //www.freelists.org/archives/si-list
 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts:

  • » [SI-LIST] SI Special Session in IEEE EMC 2012 International Symposium - Ye, Chunfei