**Browse: **Last Month: 06-2012 Main Archive Page Next Month: 08-2012

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- » [SI-LIST] Looking for IBIS model - mydiginet
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Vinu Arumugham
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - steve weir
- » [SI-LIST] Re: Looking for IBIS model - cf yee
- » [SI-LIST] Re: Looking for IBIS model - Winston Raj S T
- » [SI-LIST] Reg: Editing in IBIS model - SI
- » [SI-LIST] Re: Reg: Editing in IBIS model - steve weir
- » [SI-LIST] NEED IBIS MODEL for BU61865 - Vinothkumar D
- » [SI-LIST] Re: Reg: Editing in IBIS model - Shravan Rao
- » [SI-LIST] Fwd: Reg: Editing in IBIS model - Shravan Rao
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - heidi_barnes
- » [SI-LIST] Re: Reg: Editing in IBIS model - Craig Harabedian
- » [SI-LIST] Series termination and damping resistors - Jason Young
- » [SI-LIST] Re: Series termination and damping resistors - steve weir
- » [SI-LIST] Re: Reg: Editing in IBIS model - Lynne D. Green
- » [SI-LIST] Re: Series termination and damping resistors - Aaditya Kandibanda
- » [SI-LIST] Re: Series termination and damping resistors - Cuong Nguyen
- » [SI-LIST] Re: Series termination and damping resistors - Scott McMorrow
- » [SI-LIST] Re: Series termination and damping resistors - Tesla
- » [SI-LIST] Re: Series termination and damping resistors - steve weir
- » [SI-LIST] Re: Series termination and damping resistors - Winston Raj S T
- » [SI-LIST] Re: Series termination and damping resistors - Winston Raj S T
- » [SI-LIST] Re: Series termination and damping resistors - Todd Westerhoff
- » [SI-LIST] Re: Series termination and damping resistors - Ravinder . Ajmani
- » [SI-LIST] AC Coupling Cap Voids Questions - Dan
- » [SI-LIST] Re: AC Coupling Cap Voids Questions - steve weir
- » [SI-LIST] Re: AC Coupling Cap Voids Questions - Yuriy Shlepnev
- » [SI-LIST] Re: AC Coupling Cap Voids Questions - Scott McMorrow
- » [SI-LIST] Re: Series termination and damping resistors - Siddharth Rajagopalan
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Vinu Arumugham
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - steve weir
- » [SI-LIST] Number of bits required for BER simulation? - mark
- » [SI-LIST] Re: Number of bits required for BER simulation? - Antonis Orphanou
- » [SI-LIST] Re: Number of bits required for BER simulation? - Vinu Arumugham
- » [SI-LIST] Re: Number of bits required for BER simulation? - Todd Westerhoff
- » [SI-LIST] Number of bits required for BER simulation? - Dmitriev-Zdorov, Vladimir
- » [SI-LIST] Re: Number of bits required for BER simulation? - Asbenson, Lyndell L
- » [SI-LIST] PCB material selection and stackup optimization - Bill Hargin \(ICD\)
- » [SI-LIST] DDR3 Multi rank -ODT - Balamanikandan K
- » [SI-LIST] Re: DDR3 Multi rank -ODT - Hermann Ruckerbauer
- » [SI-LIST] spice RLC extraction of nets based on GDS2 file - jan . vercammen1
- » [SI-LIST] R: spice RLC extraction of nets based on GDS2 file - gianguida@xxxxxxxx
- » [SI-LIST] SI Engineer - Neely, Mark
- » [SI-LIST] 回复： DDR3 Multi rank -ODT - John Lee
- » [SI-LIST] Intel List of Recommeded Reading - Signal Integrity - Lora Abbe
- » [SI-LIST] Re: Alan Turing Centenary tomorrow, June 23rd - agathon
- » [SI-LIST] the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance - Tang, Linda (Xin Cai)
- » [SI-LIST] AW: the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance - Havermann, Gert
- » [SI-LIST] Re: the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance - Winston Raj S T
- » [SI-LIST] Re: the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance - Winston Raj S T
- » [SI-LIST] Re: the relationship between odd mode impedance,even mode impedance, differential impedance and common impedance - Tang, Linda (Xin Cai)
- » [SI-LIST] how can impedance effect insertion loss - liufeng1(刘丰)
- » [SI-LIST] Re: how can impedance effect insertion loss - Havermann, Gert
- » [SI-LIST] Re: Intel List of Recommeded Reading - Signal Integrity - peggi Valentia
- » [SI-LIST] Re: how can impedance effect insertion loss - Loyer, Jeff
- » [SI-LIST] How to send data over DC power - Joel Brown
- » [SI-LIST] Re: How to send data over DC power - Eric F. Steimle
- » [SI-LIST] Re: How to send data over DC power - Randy Dawson
- » [SI-LIST] Re: How to send data over DC power - O. Laney
- » [SI-LIST] Re: Intel List of Recommeded Reading - Signal Integrity - Lora Abbe
- » [SI-LIST] Re: Intel List of Recommeded Reading - Signal Integrity - O. Laney
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Cheng, Chris
- » [SI-LIST] AW: Re: how can impedance effect insertion loss - Havermann, Gert
- » [SI-LIST] Peaks and Nulls in spectral density - Aaditya Kandibanda
- » [SI-LIST] EPEPS-2012 Final Paper Submission Deadline Extension to 27th July 2012 - EPEPS Admin
- » [SI-LIST] Re: Peaks and Nulls in spectral density - Antonis Orphanou
- » [SI-LIST] Re: Peaks and Nulls in spectral density - Dhamija, Naresh
- » [SI-LIST] Re: Peaks and Nulls in spectral density - A. Ingraham
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Liuluping
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Liuluping
- » [SI-LIST] Global EMC and SI University at 2012 IEEE EMC Conf - Eric Bogatin
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Vinu Arumugham
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - steve weir
- » [SI-LIST] Re: PCB material selection and stackup optimization - Bill Hargin \(ICD\)
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Vinu Arumugham
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - steve weir
- » [SI-LIST] Re: Questions on Reference Planes for DDR3 signals - Vinu Arumugham
- » [SI-LIST] Auto-response - kundanchand chand
- » [SI-LIST] Re: Peaks and Nulls in spectral density - Aaditya Kandibanda
- » [SI-LIST] Re: Series termination and damping resistors - Aaditya Kandibanda
- » [SI-LIST] Job Posting for SI Engineer - Randon Richards (rkrichards)
- » [SI-LIST] Re: Job Posting for SI Engineer - jo rseas
- » [SI-LIST] vias and current pathes - Herbert
- » [SI-LIST] Re: vias and current pathes - Aaditya Kandibanda
- » [SI-LIST] Re: vias and current pathes - Herbert
- » [SI-LIST] Re: vias and current pathes - Aaditya Kandibanda
- » [SI-LIST] Re: vias and current pathes - Herbert
- » [SI-LIST] Re: vias and current pathes - Beal, Weston
- » [SI-LIST] Re: vias and current pathes - Antonis Orphanou
- » [SI-LIST] Re: vias and current pathes - Herbert
- » [SI-LIST] Re: vias and current pathes - Herbert
- » [SI-LIST] Re: vias and current pathes - Antonis Orphanou
- » [SI-LIST] Re: vias and current pathes - Antonis Orphanou
- » [SI-LIST] Re: vias and current pathes - Brad Brim
- » [SI-LIST] Re: vias and current pathes - O. Laney
- » [SI-LIST] Re: vias and current pathes - Rick Collins
- » [SI-LIST] Re: vias and current pathes - steve weir
- » [SI-LIST] Re: vias and current pathes - O. Laney
- » [SI-LIST] Just a simple question - Herbert
- » [SI-LIST] Re: Just a simple question - Tom Dagostino
- » [SI-LIST] AW: Just a simple question - Havermann, Gert
- » [SI-LIST] Re: AW: Just a simple question - Wolfgang.Maichen
- » [SI-LIST] Re: Just a simple question - steve weir
- » [SI-LIST] Re: AW: Just a simple question - vinod ah
- » [SI-LIST] Re: AW: Just a simple question - Wolfgang.Maichen
- » [SI-LIST] Re: AW: Just a simple question - vinod ah
- » [SI-LIST] XGMII is electrically limited to distances of approximately 7 cm - Balamanikandan K
- » [SI-LIST] AW: XGMII is electrically limited to distances of approximately 7 cm - Havermann, Gert
- » [SI-LIST] Re: Just a simple question - hws
- » [SI-LIST] Re: Just a simple question - hws
- » [SI-LIST] Re: AW: Just a simple question - hws
- » [SI-LIST] Re: AW: Just a simple question - hws
- » [SI-LIST] an unusual use for and ESD simulator - Doug Smith
- » [SI-LIST] PCB material selection Webinar (Tues.), and "Reflections and Impedance Matching" (Weds.) - Bill Hargin \(ICD\)
- » [SI-LIST] Re: AW: Just a simple question - steve weir
- » [SI-LIST] Re: AW: Just a simple question - afu
- » [SI-LIST] Re: AW: Just a simple question - steve weir
- » [SI-LIST] Re: AW: Just a simple question - O. Laney
- » [SI-LIST] Re: AW: Just a simple question - afu
- » [SI-LIST] Re: AW: Just a simple question - Herbert
- » [SI-LIST] Re: AW: Just a simple question - steve weir
- » [SI-LIST] Sr. SI Engineer (Backplane Architect) needed at Huawei in Santa Clara, CA; - Mark Apton
- » [SI-LIST] Re: Just a simple question - Brian Rautio
- » [SI-LIST] Re: Just a simple question - Wolfgang.Maichen
- » [SI-LIST] MOV rating - bala
- » [SI-LIST] Re: MOV rating - steve weir
- » [SI-LIST] Re: MOV rating - Winston Raj S T
- » [SI-LIST] AW: Re: AW: Just a simple question - Havermann, Gert
- » [SI-LIST] Re: MOV rating - Mahesh Linge
- » [SI-LIST] DDR3 Clock differential signal termination - Tesla
- » [SI-LIST] Re: AW: Just a simple question - Antonis Orphanou
- » [SI-LIST] Re: DDR3 Clock differential signal termination - Hermann Ruckerbauer
- » [SI-LIST] Re: DDR3 Clock differential signal termination - Rose, Michael
- » [SI-LIST] Re: DDR3 Clock differential signal termination - Moran, Brian P
- » [SI-LIST] Do you need to do DDR VT test? and how? - jackle zheng
- » [SI-LIST] 回复: Reg: Editing in IBIS model - tangchaojie
- » [SI-LIST] Signal Integrity Opportunity @ Apple - Sandy Perlman
- » [SI-LIST] Re: Signal Integrity Opportunity @ Apple - Aubrey Sparkman
- » [SI-LIST] Re: Signal Integrity Opportunity @ Apple - Sandy Perlman
- » [SI-LIST] relationship between reeceiver jitter transfer and jitter tolerance - Cheng, Chris
- » [SI-LIST] Re: Intel List of Recommeded Reading - Signal Integrity - peggi Valentia
- » [SI-LIST] free book better than $40 one? - O. Laney
- » [SI-LIST] Re: free book better than $40 one? - Hermann Ruckerbauer
- » [SI-LIST] Re: free book better than $40 one? - Jory McKinley
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Jory McKinley
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - mark
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Cheng, Chris
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Jory McKinley
- » [SI-LIST] Re: DDR3 Clock differential signal termination - Tesla
- » [SI-LIST] DDR3 CMD/ADD/CTL signal line termination - Tesla
- » [SI-LIST] Re: DDR3 Clock differential signal termination - Dhamija, Naresh
- » [SI-LIST] Switcher Efficiency Optimization - Tayyab Rahimkhan Pathan
- » [SI-LIST] Re: Switcher Efficiency Optimization - O. Laney
- » [SI-LIST] Re: Switcher Efficiency Optimization - bala
- » [SI-LIST] Re: Switcher Efficiency Optimization - Gene Glick
- » [SI-LIST] Re: Switcher Efficiency Optimization - Rose, Michael
- » [SI-LIST] TML excitation_A very simple question - Tesla
- » [SI-LIST] Re: Switcher Efficiency Optimization - Joel Brown
- » [SI-LIST] Request for suggestions on developing SI/PI skills - Riley, Jonathan
- » [SI-LIST] Re: Switcher Efficiency Optimization - Stefan Milnor
- » [SI-LIST] Re: Request for suggestions on developing SI/PI skills - Aaditya Kandibanda
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Vinu Arumugham
- » [SI-LIST] Length Matching for Interlaken and CFP Trace - Dan
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Vinu Arumugham
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Cheng, Chris
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Vinu Arumugham
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Cheng, Chris
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - Jory McKinley
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - T.K. Jeon
- » [SI-LIST] Re: relationship between reeceiver jitter transfer and jitter tolerance - an wage
- » [SI-LIST] AW: Re: relationship between reeceiver jitter transfer and jitter tolerance - Havermann, Gert
- » [SI-LIST] Re: Length Matching for Interlaken and CFP Trace - Jory McKinley
- » [SI-LIST] Re: Length Matching for Interlaken and CFP Trace - Jory McKinley
- » [SI-LIST] SI Special Session in IEEE EMC 2012 International Symposium - Ye, Chunfei
- » [SI-LIST] Re: Length Matching for Interlaken and CFP Trace - Dan
- » [SI-LIST] Thermal Profile WITHIN a trace - dbrooks9