[SI-LIST] [SI_LIST] Rj pattern Dependency
- From: vinod ah <ah.vinod@xxxxxxxxx>
- To: SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Fri, 5 Jul 2013 12:41:37 +0530
Hi All,
I am seeing one more weird issue on Jitter. Below is the same.
I am trying to do PCIE3 Add-in card eye calibration to meet eye height
of 46mV & eye width of 41ps. So i had to set Rj to 30% UI & Sj to 17%
UI @ 8Gbps on BERT to meet the eye width spec for testing PCIe3 Rx
circuitry.
What i see is when i change the pattern in BERT from
PCIE_A_ComplianceP7_B_Keep.ram to PCIE_modified_Compliance_Lane0.ram,
i see Rj value shooting up from 2.4ps rms to 9ps rms !!!!. The setup
is untouched during the change of pattern. In fact i get 2.4ps rms Rj
in oscilloscope/SIGTEST with clock pattern with same setup.
Also measured the BERT output directly, there I still see ~2.4ps rms
Rj (irrespective of pattern used), but when i pass the signal through
test setup (BERT--> Riser card --> CBB3 --> CLB3 --> Scope), i see
increase in Rj with pattern change. Riser card + CBB3 + CLB3 is
passive 20dB loss FR4 channel and no power src is connected to these.
As channels cannot introduce Rj, where is the extra Rj coming from? Is
there any pattern dependency along with channel effects is causing
this increase in Rj or is it Jitter post processing tool getting
confused with Rj & Dj in this scenario after signal going through the
20dB channel?
I am using SIGTEST as well as Jitter decomposition software in scope
and both the results match.
Regards
Vinod A H
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