[SI-LIST] Re: SDRAM Timing Help
- From: Penelope kaak <penelope.kaak@xxxxxxxxx>
- To: jory_mckinley@xxxxxxxxx, "Perrow, Shane" <Perrow@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 21 Sep 2007 09:37:34 -0700 (PDT)
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Jory McKinley <jory_mckinley@xxxxxxxxx> wrote:
Hello Shane,
Your skew numbers provided by the chip vendor (tsdSDOS and tsdSDOH) are worst
case for a range of operating frequencies. Your range of operating frequencies
for a given set of skew numbers is not that large due to the dynamics of the
PLL.
If your chip operated 1Mhz your skew numbers would be much different than say a
chip operating at 100Mhz due to the PLL dynamics.
The basic formula for data tco numbers for a single edge clock look ok.
-Jory
----- Original Message ----
From: "Perrow, Shane"
To: Jory McKinley ; si-list@xxxxxxxxxxxxx
Sent: Thursday, September 20, 2007 12:32:38 AM
Subject: RE: [SI-LIST] SDRAM Timing Help
Thanks Jory.
It's not DDR so I guess the only difference may be;
tco_min = tsdSDOH
tco_max = clk_period - tsdSDOS
However, this suggests that when dropping the clk rate down to say 1MHz,
the tco_max becomes several hundreds of nS!!!
Shouldn't the tco_max parameter be independent of the clock rate?
Thanks again.
Shane.
-----Original Message-----
From: Jory McKinley [mailto:jory_mckinley@xxxxxxxxx]
Sent: Thursday, 20 September 2007 2:32 PM
To: Perrow, Shane; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] SDRAM Timing Help
Hello Shane,
This is done to account for internal PLL jitter plus any skew. Assuming
double data rate (data output on every clock edge) your general tco
numbers:
tco_min = tsdSDOH
tco_max = 0.5*clk_period - tsdSDOS
Draw out a timing diagram to convince yourself.
-Jory
----- Original Message ----
From: "Perrow, Shane"
To: si-list@xxxxxxxxxxxxx
Sent: Wednesday, September 19, 2007 7:52:07 PM
Subject: [SI-LIST] SDRAM Timing Help
Hi all,=20
I'm hoping someone can help.
I'm trying to determine some min and max trace lengths to provide a safe
setup and hold margin for a CPU-SDRAM interface.
My problem is that all timing analysis usually refers to the parameters
tco_min and tco_max, but in this case the CPU provides the SDRAM clock
(with an internal PLL).=20
The CPU does not specify tco parameters for SDRAM writes, it specifies
tsdSDOS and tsdSDOH, which are defined as "output setup and hold times".
On the timing diagram this indicates that data is setup before the clock
edge and held after the clock edge for a certain amount of time.
My question is - how do these parameters tsdSDOS and tsdSDOH correlate
to the standard tco_min and tco_max ????=20
Thankyou in advance :)
=20
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