[SI-LIST] SDRAM PCB Layout
- From: Gene Glick <gglick@xxxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Apr 2010 15:59:15 -0400
Hi,
I am working on an Atmel AT91SAM9260 processor with SDRAM running at
around 100MHz (or maybe it's 133, off the top of my head). My board is
4 layers, 2 routing, 1 power, 1 ground. I have a couple of questions,
sort of general principals . . .
1. Atmel offered up an app note that shows *all* of the SDRAM signals
series terminated, with 27 ohms. I don't believe it is that way on
their eval board, but I didn't double check. Question is, are they all
really necessary? Yes, I realize much more to this question, how long
the traces for example. My plan is to terminate the clock line only.
Bad idea?
2. I see from their app note that they traverse layers all over the
place. In fact, the SDRAM and uP are not on the same side of the board.
Although I hadn't considered doing it this way, it appears to make a
tighter layout. In any case, every signal changes sides at least once.
On general principles, I think this is less optimal - but ok? My
current layout, has uP and SDRAM on same side. Footprint is slightly
larger than Atmel app note shows, but fewer layer transitions, many
signals reside on top-side only.
3. Atmel won't comment on routing strategies, but I was wondering if
the it is ok to have the clock do something like this (hopefully ascii
drawing works out):
Layer 1: SDCLK_OUT -| SDRAM1-| SDRAM2-|
Layer 2: | | |
Layer 3: | | |
Layer 4: |--------------------------------------{TERMINATOR}
thanks
gene
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