[SI-LIST] Re: SDRAM PCB Layout
- From: "Nick Luther" <Nick.Luther@xxxxxxxxxx>
- To: "Gene Glick" <gglick@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 30 Apr 2010 09:46:32 -0500
Hi Gene,
I completed a successful design with an AT91SAM9261 where every DQ was
series-terminated at the SDRAM and SDCK was terminated at the MCU. I
don't believe we terminated our address lines--our simulation must have
shown the MCU drive strength to be acceptable. Our design was atypical
and had some other timing challenges to overcome because we needed to
use Mobile SDRAM, but we were able to find a solution in simulation and
when we powered it up it worked. Also, we only had one SDRAM IC, so
that's a pretty significant difference. I don't remember all of the
stackup details, but it was about eight layers, standard technology,
with memory routing on L2-L3 referenced to L1 or L4. The routes were
short.
I wasn't able to do any serious correlation on that project, so I can't
vouch for the IBIS files. I can state that they are available from
Atmel, and I'm sure they're also available from your memory vendor.
I've also seen another design in the family where the series terms were
not included initially and the engineers decided to put them back in
after making some measurements. I wasn't involved in that project so I
don't have much more insight besides that high-level observation.
Have you completed a pre-route simulation? It served us well on this
project.
I have some other technical comments on the part related to SDRAM
timing. Feel free to call.
Take care,
Nick
--
Nick Luther
Design Engineer
Plexus Technology Group
55 Jewelers Park Drive
Neenah, Wisconsin 54956 USA
Tel +1 920-969-6392
Fax +1 920-720-6707
Nick.Luther@xxxxxxxxxx
http://www.plexus.com/
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Stephen Zinck
Sent: Friday, April 30, 2010 12:01 AM
To: 'Gene Glick'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM PCB Layout
Hi Gene,
I am not sure whether the Atmel device provides you with output
drive-strength control or not. A lot of times the memory controller
portion
of these devices has several drive strength/slew-rate options so that
the
customer-base can design the interface with a variable number of SDRAM
device loads. If so, the output drive strength can possibly be set such
that
no external series terminations are required at the memory controller
source
(although signal integrity simulations should verify this). Most of the
time, the SDRAM drive strength is significant, and as such, requires a
source series termination at the SDRAM.
The topology you reference below didn't come through clearly. But I
believe
this is a source series, daisy-chain topology. Clearly the clock signal
will
transition at different times at each SDRAM, if this is the case. You
will
need to take this into account in your timing analysis. For an interface
such as this, a "T" topology might serve you well. The nature of the "T"
topology, and having two loads, may actually reduce the need for series
terminations as well...
Via transitions, from one side of the board to the other, are typically
fine. Your stack-up doesn't seem to present much potential for via
stubbing
effect. I think you are probably OK.
Best regards,
Steve
Stephen P. Zinck
High-Speed Signal Integrity Consulting
Interconnect Engineering Inc.
P.O. Box 577
South Berwick, ME 03908
Phone - (207) 384-8280
Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
Web - www.interconnectengineering.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Gene Glick
Sent: Thursday, April 29, 2010 3:59 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM PCB Layout
Hi,
I am working on an Atmel AT91SAM9260 processor with SDRAM running at
around 100MHz (or maybe it's 133, off the top of my head). My board is
4 layers, 2 routing, 1 power, 1 ground. I have a couple of questions,
sort of general principals . . .
1. Atmel offered up an app note that shows *all* of the SDRAM signals
series terminated, with 27 ohms. I don't believe it is that way on
their eval board, but I didn't double check. Question is, are they all
really necessary? Yes, I realize much more to this question, how long
the traces for example. My plan is to terminate the clock line only.
Bad idea?
2. I see from their app note that they traverse layers all over the
place. In fact, the SDRAM and uP are not on the same side of the board.
Although I hadn't considered doing it this way, it appears to make a
tighter layout. In any case, every signal changes sides at least once.
On general principles, I think this is less optimal - but ok? My
current layout, has uP and SDRAM on same side. Footprint is slightly
larger than Atmel app note shows, but fewer layer transitions, many
signals reside on top-side only.
3. Atmel won't comment on routing strategies, but I was wondering if
the it is ok to have the clock do something like this (hopefully ascii
drawing works out):
Layer 1: SDCLK_OUT -| SDRAM1-| SDRAM2-|
Layer 2: | |
|
Layer 3: | |
|
Layer 4:
|--------------------------------------{TERMINATOR}
thanks
gene
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