[SI-LIST] Re: Rise / Fall time
- From: Zack B <zacksilist@xxxxxxxxx>
- To: Joseph.Schachner@xxxxxxxxxx
- Date: Tue, 1 May 2012 15:13:30 +0100
Hi Joe,
Thanks for the reply. As stated in my initial post, I'm trying to arrive at
the critical length and hence the rise / fall times are quite important.
Before I simulate, the tool estimates the switching times (based on IBIS)
as 0.240 ns. And, when I simulate and measure the rise/fall time at the
driver, the value is 0.850 ns. In this case, there is no degradation as
both measurements are at the driver. As there are two different values of
the rise time for the same driver, my critical lenght also varies. So, is
my technique right?
Zack
On Tue, May 1, 2012 at 2:59 PM, <Joseph.Schachner@xxxxxxxxxx> wrote:
> Re "the switching time automatically reported for my
>
> address signals are 0.240 ns. However, when I simulate, the rise and fall
> times values are in 0.850 ns range. There is a similar discrepancy for my
> data signals too. Any idea why is the difference?
> "
>
> I'm not sure what Hyperlinx can show you before you simulate. I suspect
> (just a guess) that it is showing you the rise time it is going to create
> at the source of that signal. I don't exactly know what's in the signal
> path in your simulation between that source and where the 0.850ns is
> reported, but that 0.850ns number surely includes the degradation due to
> that path.
>
> You should ask someone who knows more about Hyperlinx if my guess is
> correct.
>
> If this is not just a Hyperlinx question, and you are asking "what
> degrades rise time like this?" ... that's a much more interesting
> question, and I recommend Eric Bogatin's book "Signal Integrity Simplified"
> which he recently updated to include power distribution networks. Some of
> the things that cause rise times to degrade:
>
> 1) increasing loss with frequency ... some materials are worse than
> others, FR4 is pretty horrible.
> 2) different propagation speed in air and in the board material, in
> microstrip traces - stretches transitions.
> 3) any impedance discontinuities (ie, vias?) may cause reflections
> (reflected energy), so it will take longer for the signal to reach its
> final value at the end of the path.
> 3a) at very fast rise times, the woven construction of FR4 causes
> impedance ripples as the wave front passes over just resin, then over a
> fiberglass bundle in resin, then over just resin, etc.
> 4) inductance - for example, the connection from the internal IC pad to
> the pin and down the pin to the board ... may be a serious issue. Can be
> mitigated somewhat, see the book I recommended.
> 5) Skin effect. Very high frequencies are carried only near the outer
> surface of a trace, increasing ohmic resistance. Probably not a
> significant issue, compared to those mentioned above.
>
> If you don't want to read a book, there is LOTS of information about these
> topics on the web, much of it mentioned in previous SI-LIST posts.
>
> --- Joe S.
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