if some one is using 3D EM field solver, modeling of s-parameter involves
some additional process in these kind of problems.
1) setup the ports on signal nets as always done..
2) set the ports on capacitors pad as well. select the capacitors near the
applicable signal trace for related and unrelated power plane.
3) run the field solver and extract s-parameter model. this simulation will
take lot of time as per EM problem size.
4) bring this s-parameter model in circuit simulator (ADS, hspice or any
other tool..)
5) hook the cap models on cap ports.
6) run the AC simulation in circuit simulator to see the overall
s-parameter behaviour.
EM tools does not differentiate between power & ground planes. it is just
metal plane for it. circuit simulators will better understand the behaviour
based on s-parameter extraction. simulation is definitely time consuming
using any 3D EM tool, but it may be worth spending so much simulation time.
Thanks & Regards,
Sanjeev Gupta
www.sigintegrity-solutions.com
On Thu, Jul 28, 2016 at 4:05 AM, Scott McMorrow <scottmcmorrow@xxxxxxxxx>
wrote:
Common mode injection occurs at the transition on and off the plane. The
signal is essentially crossing a split plane in the z-axis.
If the plane and power system has a sharp resonance, that resonance will be
reproduced on the differential signal. You will see it in the channel
s-parameters of the signal pair. It can become a mess. Whether it causes
data errors depends upon where in the frequency domain that the coupling
occurs. At those frequencies, all differential pair vias are coupled
together through the full wave resonance.
We see this in modeling.
We measure this.
We avoid this.
On Jul 27, 2016 4:35 PM, "Vinu Arumugham" <dmarc-noreply@xxxxxxxxxxxxx>
wrote:
The dI/dt of the differential traces will mostly cancel. Only the commonthe
mode dI/dt caused by the skew has to be accounted.
Thanks,
Vinu
On 07/27/16 13:13, Ravi Chandra Bollimuntha wrote:
Hello,
I am a rookie SI practitioner and have few questions related to this
discussion.
If the unrelated power plane is used as reference, won't the dI/dt on
andtraces which is also present on the reference power plane, at leastlocally
below the traces, cause power bounce (like ground bounce)?
And won't the large loop, that makes the mutual inductance b/w trace
powerplane cancel only negligible self inductance of the return path,exacerbate
the power bounce?
If so, is there any capacitor-placement strategy to shunt out this
leeritchey@xxxxxxxxxxxxx>noise close to where it gets generated?
Thanks,
Ravi
On Wed, Jul 27, 2016 at 11:48 AM, Lee Ritchey <
si-list-bounce@xxxxxxxxxxxxxwrote:for
My approach as well. This requires that each PDS voltage be designed
low ripple as it will couple onto signals with no attenuation.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:
]designs
whichOn Behalf Of Jeff Loyer
Sent: Wednesday, July 27, 2016 7:21 AM
To: pratapasimha@xxxxxxxxx; Si-list <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Return path on an unrelated power plane
When I looked at this for server designs, including building boards
used power reference instead of GND, I concluded that for server
copper,with lots of layers (>6) and inter-plane capacitance, copper is
thedesign).
thatsignals don't care what voltage potential they're at. The caveat was
anif you reference to a relatively high voltage (12V in our unfortunate
case), the noise from that voltage can get induced on the signals (not
withissue with differential signals). I don't have any data for designs
fewer planes that are spaced far apart (e.g., a typical 4-layer
si-list-bounce@xxxxxxxxxxxxx
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:
]as
On Behalf Of Pratap Simha
Sent: Tuesday, July 26, 2016 5:07 PM
To: Si-list
Subject: [SI-LIST] Return path on an unrelated power plane
Hi experts,
I have couple of (3GHz Nyquist) SERDES stripline traces that have GND
unrelatedDriverreference plane.
Instead of GND if I use an unrelated power (say 3.7V Main board power)
plane, will there be any impact on return path (huge loop?) in this
situation, if there is no bypass capacitors located close to either
or Receiver?
(there will be bypass capacitors on the board however for this
bypasspower, but not close to Driver or Receiver)
If I want to use an unrelated power plane as reference can I use
havereturncapacitors locating one at the driver and one at the receiver so the
path (with smaller loop) can easily be established ?
Is there a way to simulate this ? because the simulation tools only
planeoption to include a reference plane that is either GND or the VDD
of
the traces that we are simulating.
Thank you,
Pratap
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