Hello,
I am a rookie SI practitioner and have few questions related to this
discussion.
If the unrelated power plane is used as reference, won't the dI/dt on the
traces which is also present on the reference power plane, at least locally
below the traces, cause power bounce (like ground bounce)?
And won't the large loop, that makes the mutual inductance b/w trace and
plane cancel only negligible self inductance of the return path, exacerbate
the power bounce?
If so, is there any capacitor-placement strategy to shunt out this power
noise close to where it gets generated?
Thanks,
Ravi
On Wed, Jul 27, 2016 at 11:48 AM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
wrote:
My approach as well. This requires that each PDS voltage be designed for
low ripple as it will couple onto signals with no attenuation.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Jeff Loyer
Sent: Wednesday, July 27, 2016 7:21 AM
To: pratapasimha@xxxxxxxxx; Si-list <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Return path on an unrelated power plane
When I looked at this for server designs, including building boards which
used power reference instead of GND, I concluded that for server designs
with lots of layers (>6) and inter-plane capacitance, copper is copper, the
signals don't care what voltage potential they're at. The caveat was that
if you reference to a relatively high voltage (12V in our unfortunate
case), the noise from that voltage can get induced on the signals (not an
issue with differential signals). I don't have any data for designs with
fewer planes that are spaced far apart (e.g., a typical 4-layer design).
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Pratap Simha
Sent: Tuesday, July 26, 2016 5:07 PM
To: Si-list
Subject: [SI-LIST] Return path on an unrelated power plane
Hi experts,
I have couple of (3GHz Nyquist) SERDES stripline traces that have GND as
reference plane.
Instead of GND if I use an unrelated power (say 3.7V Main board power)
plane, will there be any impact on return path (huge loop?) in this
situation, if there is no bypass capacitors located close to either Driver
or Receiver?
(there will be bypass capacitors on the board however for this unrelated
power, but not close to Driver or Receiver)
If I want to use an unrelated power plane as reference can I use bypass
capacitors locating one at the driver and one at the receiver so the return
path (with smaller loop) can easily be established ?
Is there a way to simulate this ? because the simulation tools only have
option to include a reference plane that is either GND or the VDD plane of
the traces that we are simulating.
Thank you,
Pratap
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