[SI-LIST] Re: Return path for stripline between two power planes
- From: steve weir <weirsi@xxxxxxxxxx>
- To: ma.kidman@xxxxxxxxx,si-list@xxxxxxxxxxxxx
- Date: Mon, 17 Apr 2006 03:49:00 -0700
George,
This is primarily a common mode issue. I assume that the five layers
shown represent only part of your stack-up. Is VCC2 your PECL
Vcc? If not, how about moving the PECL Vcc to layer 3and adjusting
your dielectric spacing:
Vxxx or Gnd
big gap
S1
little gap
PECL VCC
little gap
S2
big gap
Vxxx or Gnd
First, there is nothing magic about "Gnd". To quote Dr.
Archambeault, ground is a place for potatoes and carrots. We are
concerned about wave guides, which means the return image path and
common mode reference voltage. If the same Vcc is used at both the
transmitter and receiver for PECL outputs and inputs, that is the
best but not only choice for the image return plane(s).
The hierarchy of return paths from most desirable to least is:
1) Single surface that matches the source and destination reference voltage.
2) Two surfaces of a single sheet that match the source and
destination reference voltage
3) Multiple surfaces tied together by stitch vias that match the
source and destination reference voltage.
4) Single surface that does not match the source and destination
reference voltage
5) Two surfaces of a single sheet that does not match the source and
destination reference voltage
6) Multiple surfaces tied together by stitch vias that do not match
the source and destination reference voltage.
7) Surfaces coupled together by interplane and bypass capacitors
The reason for the hierarchy is uncertainty. 1 is the ideal. 2 is a
very close second. 3 can be a little or a lot worse. 4-7 all rely
on capacitive coupling through cavity dielectric and bypass
capacitors. At 3GHz, a bypass capacitor with 1nH mounted inductance
looks like 20 Ohms. To the 100ps rising edge of a 3GHz serdes,
anything further than about 0.3" away from any given signal
transition through the PCB cavity does not reflect back in time to
impact an incident edge. That means a bypass cap 0.3" away is all
but pointless for the incident edge. Suppressing resonances, is a
different issue. That radius increases inversely with the spectral
components. For the 2.4nS long worst case runs in 8b10b that radius
of action likely includes most of your board. Plane geometries,
stitch via patterns, and to a smaller extent bypass capacitor loading
will determine the location and magnitude of resonances. What you
pass through the cavities particularly in terms of single ended
busses determines excitation.
If you make layer 3 your PECL Vcc it looks like you have #2 in the
bag. If you want to go another route, you have some homework to
do. Essentially, you need to determine what the impedance profile
looks like plane to plane in each of those cavities and the signal
spectra of what you will be injecting into the cavity(s) in
question. If you can tolerate both the losses that you will get for
the diff pairs going through, and the increased EMI and crosstalk
that will result from ALL of the signals you pass through those
cavities, then all is well. If you have few or no single ended
signals traversing the cavities, then there won't be that much to
mess with your diff signal common mode. Similarly, if you can get
the coupling impedance low enough between planes across your signal
spectra to tolerate whatever it is you do inject, then even 7) still
works. But, you need to figure out where you are with your signals
and those cavities first. Lee attests that he has made 7) work on
hundreds of boards. In the end, it all comes down to coefficients.
Doug Smith's most recent "Technical Tidbit" is quite germane, and
should open your eyes to some of the differences between 1) and
7). Just appreciate that on Doug's test board, there are fewer
layers than your board, no ground stitch vias and no bypass
capacitors, all of which affect the results. Also appreciate that
what he tested is susceptibility / radiation. A different test on a
different configuration will yield different results.
Additional resources include a study done by Scott McMorrow on our
website www.teraspeed.com, and a number of papers by Dr. Bruce Archambeault.
Steve.
At 01:51 AM 4/17/2006, geor_dai wrote:
>Dear All SI experts,
>
>One question regarding to return path for signals and signal quality
>concerns.
>
>If we have stripline configuration as below, a signal trace S1 between
>two power planes. Because limited routing space in the board, not all
>high speed signals can be on S2 layer, which is better for signal
>quality. So some of 2.125Gbps signals running on S1.
>
>--------VCC1
>--------S1 [2.125G PECL]
>--------VCC2
>--------S2 [2.125G PECL]
>--------GND
>
>My question is,
>When the signal S1 is transient from high to low or low to high, which
>plane would be the return path, VCC or GND? EMC/EMI impact? Any
>compensation suggestion?
>How much risk if we go to PCB fabrication like this stack up?
>
>Thanks very much!
>Best Regards,
>George
>
>
>
>
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