[SI-LIST] Re: Resonant Modes
- From: steve weir <weirsi@xxxxxxxxxx>
- To: xuzhengrong <xuzhengrong@xxxxxxxxxx>
- Date: Wed, 29 Aug 2007 12:54:50 -0700
Zhengrong, I think it is a good practice to refer to the negative supply
rail as Vss and not ground. A chunk of metal develops all kinds of EMFs
from fast currents no matter what we choose to label it.
If you want to reduce high frequency EMFs on a chunk of metal, you have
to reduce the magnetic flux density. That means changing the geometry of
the metal, or reducing the HF current you carry on it.
Steve
xuzhengrong wrote:
> Steve,
> As you said, there's more chance to emerge PI problems on less layers' PCB
> which has less or no gnd plane.
> Recently there's a 2 layer board without gnd plane, which has evident
> voltage noise on the gnd greatly , namely ground bounce, affecting the
> signaficant signs. So I want to locate this problem with EM tools.
> Generally speaking, large system boards have less problems like gnd bounce,
> for they have integral gnd planes and conduct noise to the earth ground from
> metallic bolts.
> However, terminal devices such as cell phone have no connect to the earth
> ground. Noise can be only dissipated by resistors(including ESR) or
> radiation and still left much on the board leading to more PI and SI
> problems.
> But I find that the resonance caused by cavities seems to be lesser affected
> by placing several HF caps.
> Could you give me some idea about minishing the ground bounce in such
> boards?
>
>
>
>
> -----邮件原件-----
> 发件人: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> 代表 steve weir
> 发送时间: 2007年8月29日 16:57
> 收件人: xuzhengrong
> 抄送: si-list@xxxxxxxxxxxxx
> 主题: [SI-LIST] Re: Resonant Modes
>
> Zhengrong, generally the modal impedance peaks build up to a limit and then
> fall-off for the higher modes. If your board or plane patch area is small
> the high frequency limit where this happens might be very high. If you do
> not see this fall-off you are probably not modeling dielectric loss
> correctly, have very small cavity areas, and/or very thick cavities.
>
> There are a number of ways to suppress Q. I think Istvan just put on a
> presentation for Ansoft on this subject. I haven't checked to see if his
> presentation is available to the public or not. A gross method is to flood
> the board with bypass capacitors. If many bypass capacitors are evenly
> spaced and selected with the proper values then the resonances only peak
> above the inductive line a little bit. This is a somewhat crude and
> expensive solution, but it does work. Bruce Archambeault has also written
> extensively on this subject, usually from an EMI centric point of view.
>
> The S11 impedance which is much easier to simulate than to measure tells you
> how much noise will appear at a given location for a given excitation at
> that point. Higher Qs result in higher impedance peaks, and consequently
> higher voltage noise for a given amount of current injected at the frequency
> of interest. Basically to combat the noise voltage, you either have to bring
> the PDN impedance down, and/or reduce the amount of energy you inject into
> it such as through return currents.
> HF impedance including resonant peaks always comes back to the inductance of
> the bypass caps and the interconnect which is why I give inductance a lot of
> attention. If you are trying to build cheapy line cards on 4 or 6 layers or
> even 2 layers this takes a good deal of care.
>
> You can use bypass caps to drop the cavity impedance and suppress noise
> across the card very effectively even with thick cavities. Where thick
> cavities can be very ugly is when using ICs that were not engineered to work
> well on high PDN impedance PCBs. Getting IC manufacturers to design ICs with
> the application PCB in mind is still largely a work in progress. In extreme
> cases an IC may not be engineered properly to work on any realizable PCB.
>
> Steve.
>
> xuzhengrong wrote:
>
>> Steve,
>> I'm very glad to receive your reply and have learnt a lot from your
>> papers issued on DesignCon.
>> I know increasing ESR and decreasing inductance can lower Qs which
>> decreases the resonance and makes the impedance smooth.
>> What I meant is that, for the same plane pair structure with the same
>> capacitors, when I set the number of modes and simulate, I will get
>> datas of different mode such as Mode 1, Mode2 and so on.
>> According to the figure of the result, it seems that Mode 1 shows the
>> resonance from horizontal angle, Mode 2 from vertical angle, Mode 3
>> from diagonal angle, etc. Different mode analyzes the resonance from
>> different angle.
>> As my last mail said, every mode has a certain frequency and Q
>> increases with the number of modes and corresponding frequency in term of
>>
> the result.
>
>> Mode 1 is the lowest frequency among all. Therefore, with the
>> increasement of the number of modes, more resonant frequency will appear.
>> You mean, I only pay attention to the bandwidth of significant signal
>> which may excite the resonance. Ok, I see.
>>
>> My following question is, why do Qs increase with the number of modes
>> and frequency for the same cavity and PDN?
>> Which imformation will I obtain from Qs?
>> For Q indicates the ratio of storage and loss, does it mean larger
>> number of Mode with higher resonant frequency will let more energy pass?
>>
>> Best Regards
>> Zhengrong Xu
>>
>>
>> -----邮件原件-----
>> 发件人: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> 代表 steve weir
>> 发送时间: 2007年8月29日 14:02
>> 收件人: xuzhengrong@xxxxxxxxxx
>> 抄送: si-list@xxxxxxxxxxxxx
>> 主题: [SI-LIST] Re: Resonant Modes
>>
>> Zhengrong,
>>
>> Pay attention to the resonances that are within the bandwidth of
>> significant signal energy from your loads and/or injected into your return
>>
> path.
>
>> Q depends on the capacitors and materials you use for your PCB. Low
>> mounted inductance capacitors such as X2Ys exhibit lower Qs than
>> capacitors with higher mounted inductances and similar ESRs.
>>
>> Cavities that are thinner and/or have higher tangent losses exhibit
>> lower Qs than do thicker cavities and/or cavities with lower tangent loss.
>>
>> At the end of the day you are always fighting inductance in your
>> capacitors and interconnect. You can manipulate modes and Q by
>> manipulating your capacitors and cavity geometries.
>>
>> Steve.
>>
>> xuzhengrong wrote:
>>
>>
>>> Oh, I am so sorry for that.=20
>>> I have sent another email in text format, but i don't know why it =
>>> hasn't been sent to all yet.
>>> When I sent to si-list@xxxxxxxxxxxxx, i received several
>>> autoreplies = for their out of office.=20 So I sent both to
>>> si-list@xxxxxxxxxxxxx and = si-list-bounce@xxxxxxxxxxxxx this time.
>>> I'm new here and very glad to join in.=20 Could you tell me the
>>> relationship between si-list@xxxxxxxxxxxxx and
>>> si-list-bounce@xxxxxxxxxxxxx? When i want to join the discussion,
>>> which = mail address will i send to?
>>>
>>> Thank you for your reminder with best regards.=20 My question is
>>> listed as follows.
>>>
>>>
>>> Hi all,
>>> I am new in using EM tools to analyze the plane pairs' resonance.
>>> After inputing the number of modes and computing, the results have =
>>> several values including freqency and Q. Every mode has a certain
>>> frequency and = Q increases with the number of modes.=20 =20 Which
>>> mode should i pay most attention to?
>>> Why does Q value increase with the number of modes and frequency?
>>> How to analysze with these data and which information can i obtain
>>> from = it?
>>> =20
>>> Appreciate any idea about that.
>>> =20
>>> Best Regards
>>> Zhengrong Xu
>>>
>>>
>>>
>>> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
>>> =B7=A2=BC=FE=C8=CB: olaney@xxxxxxxx [mailto:olaney@xxxxxxxx]=20
>>> =B7=A2=CB=CD=CA=B1=BC=E4: 2007=C4=EA8=D4=C229=C8=D5 12:00
>>> =CA=D5=BC=FE=C8=CB: xuzhengrong@xxxxxxxxxx
>>> =D6=F7=CC=E2: Re: [SI-LIST] Resonant Modes
>>>
>>> Just so you know what I actually received...
>>> I think jpg files need to be sent as attachments.
>>>
>>> On Wed, 29 Aug 2007 11:02:59 +0800 xuzhengrong
>>> <xuzhengrong@xxxxxxxxxx>
>>> writes:
>>>
>>>
>>>
>>>> Content-type: text/plain; charset=3Dgb2312
>>>> Content-transfer-encoding: base64
>>>>
>>>>
>>>>
>>>>
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>>> mUg
>>>
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>>>> IGFuZCBkZWxldGUgaXQhDQoNCiANCg=3D=3D
>>>> =20
>>>> =20
>>>> =20
>>>> -- Binary/unsupported file stripped by Ecartis --
>>>> -- Type: image/jpeg
>>>> -- File: outlook_huawei_logo_cn.jpg
>>>> =20
>>>> =20
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>>
>>
>
>
> --
> Steve Weir
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
>
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
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(707) 780-1951 Fax
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