In addition to what Istvan said, also acknowledge that in the lamination
process of the pcb during fab, the thickness of the prepreg will reduce from
heat pressing. How much reduction there is could be somewhere in the ball park
of a few tenths of a mil to half a mil. This largely depends on the board
manufactuer's process/capabilities and the Cu patterns on the layers adjacent
to each other separated by the prepreg. Generalizing, three scenarios could be
signal-against-signal, signal-against-plane, and plane-against plane.
It's a good habit to speak with a board house you're intending to use about
this issue.
-Ryan
Sent from my Verizon 4G LTE Smartphone
------ Original message------
From: Istvan Novak
Date: Mon, Apr 17, 2017 6:08 AM
To: chetanreddy179@xxxxxxxxx;si-list@xxxxxxxxxxxxx;
Subject:[SI-LIST] Re: Regarding
Hi Chetan,
Using the dielectric constant of the resin in the adjacent prepreg is a
reasonably start.
Keep in mind that for physical length matching this value is irrelevant.
For electrical length (delay) matching it may have a second-order effect.
Regards,
Istvan Novak
Oracle
On 4/17/2017 6:32 AM, chetan reddy wrote:
Hi Experts,
i have a doubt in entering stackup into PCB designers for length matching
calculations. What should i enter dielectric material fill in the conductor
layers? is it the adjacent dielectric layers properties(Dk) values or epoxy
resin(Dk)?
Please kindly help me in clarifying.
Regards
Chetan
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
