Hello Doug,
nice report, but I have some questions and some remarks.
First the questions:
-Why is the bottom trace cooler than the Top trace? (must be some boundary
setting as the traces are the same size, right?)
-Which Thermal boundary has been used?
Remarks:
I think the conclusions aren't precisely pronounced and can be misunderstood.
Your test showed that the 10 mil via is not the thermal bottleneck when the
trace is wide enough for the current. This is purely based on a test vehicle
without Co-heating and with traces running on outer Layers. In these (rare)
cases, the trace will act as a heatsink, cooling away the heat created by the
via. But still the via creates heat, and in more dense designs and higher
currents the heat is not transferred to the air, and you will see higher
temperature rises at vias as each via will heat up the surrounding vias and
traces (called Co-heating). The conclusion that no via can be small enough to
burn up (that’s what it sounds when you state: the current will not heat up a
via)
The same behavior is seen in connectors, where the tiny contact point is cooled
by the Mass of the contact and the Copper cable and traces attached to the
contact. But as soon as you add mode contacts into a tiny housing, the cooling
effect drops dramatically. Many designers don't take co-heating into account,
and then the connectors burn away due to overheating even though each single
contact was derated to carry a the amount of current that was applied to it,
but the derating was done for individual contacts.
BR
Gert
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Doug Brooks
Sent: Thursday, March 17, 2016 3:14 PM
To: lekannat@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Recommendations on Current Carrying Capacity of Vias on
PCB's
Very timely question.
Check out the article that appeared in the Feb issue of PCD&F "Empirical
Confirmation of Via Temperatures." Here is a link:
http://www.pcdandf.com/pcdesign/index.php/magazine/10604-thermal-modeling-1602
The answer is that via temperature is NOT determined by via current. The reason
is that the thermal coupling s so good between the trace and the via that as
long as the trace is sized correctly, the via cannot overheat. Therefore, only
a single small via is required.
I will be speaking to the local Designer's Council (Seattle) tentatively
scheduled for May 4th. Also watch for a new book on this topic to be published
and available on Amazon by the end of April.
Leojik Kannathara wrote:
Hi Experts,
I am working on PowerDC simulation of PCB's and would like to understand if
there is a general guidance on the current carrying capacity of vias. I have
been going through IPC 2152 to understand if I can correlate via sizes to
current carrying capacity, but I am not able to make a clear correlation.
Are there rules of thumbs or a via size to current (in Amps) correlation /
specific literature in this area that people in the industry could point me
too ?
Are there differentiation on current carrying capacity based on different
types of visa - buried, through, micro vias ?
Regards,
Leojik Kannathara
Signal Integrity Engineer
Microsoft
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