Abhishek,
Frequently when we are pushed towards lowest cost and maximum features, we
tend to have designs which tend to push limits.
Saturn provides guidelines which are somewhat conservative. Hence, beyond
the guideline we need to fine tune based on our actual layout features.
Regards
Surjendra
On Thu, Mar 17, 2016 at 10:36 AM, Gupta, Abhishek <Abhishek.Gupta@xxxxxxxxx>
wrote:
Hello,
In such situation I would preferably use tool like "Saturn PCB toolkit".
It considers IPC2152 for calculation's and can be used for blind/buried too.
Most important, it's free.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Leojik Kannathara
Sent: 17 March 2016 00:02
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Recommendations on Current Carrying Capacity of Vias on
PCB's
Hi Experts,
I am working on PowerDC simulation of PCB's and would like to understand
if there is a general guidance on the current carrying capacity of vias. I
have been going through IPC 2152 to understand if I can correlate via sizes
to current carrying capacity, but I am not able to make a clear correlation.
Are there rules of thumbs or a via size to current (in Amps) correlation /
specific literature in this area that people in the industry could point me
too ?
Are there differentiation on current carrying capacity based on different
types of visa - buried, through, micro vias ?
Regards,
Leojik Kannathara
Signal Integrity Engineer
Microsoft
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