[SI-LIST] RapidIO timing
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 28 Mar 2005 08:54:35 -0700
I'm a little confused with the timing of RapidIO.
At some point before the receiving flop the source synchronous clock or data
must be shifted in order to allow for setup and hold time.
Theoretically, this shifting can be done at the transmitter, on the board,
or at the receiver.
The part I'm confused with is that the RapidIO requirement seems to limit
this shifting to the receiver only. I'm basing this on the receiver
"Tskew,pair" parameter and the way that it's defined in figure 8-8 of the
spec ("Data to Clock Skew"). A close look at this rule implies a very
aligned clock edge and data edge (if I'm reading it correctly). In order to
meet this, the shift must be done afterwards.....
Can one of you RapidIO wizards help clarify this?
Also, I'm looking for a good paper on this subject (Receive clocking of
RapidIO).
thanks,
Jim Peterson
Honeywell
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
