[SI-LIST] Re: DDR Termination
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 28 Mar 2005 05:58:28 -0700
Besides the ones already mentioned, the main difference I have seen with not
including the pullup terminations to Vtt is that the DDR SSTL2 drivers will
give you a full swing signal (from 0v to 2.5v).
Using the series and pullup together gives you a voltage swing that is more
than 50% reduced. A smaller voltage swing will reduce many of your SI
problems.
As mentioned, you do take a power hit with the pullups, and that can be
painful with wide buses.
regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Friday, March 25, 2005 2:41 PM
To: SSantangelo@xxxxxxxxxxxx; Dan Bostan; scott@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Termination
Steve, there are two issues:
1) Do you have latent energy from preceding cycles rattling around the
channel. AND
2) Do the drivers run rail to rail on each cycle.
In the case of 1) as long as the channel is short enough, and you dissipate
the energy on a cycle by cycle basis, you will not have ISI issues. 2) Can
be more insidious. It basically makes for group delay, sic ISI that is
run-length dependent. If you run a string of 1's the channel AC zero shifts
towards 2.5V, and if you run a bunch of zeroes towards 0V. This alters the
delay time from an arbitrary reference point to the logic crossing to the
opposite bit level for the first bit after the long run.
When in doubt simulate!
Steve
At 02:31 PM 3/25/2005 -0500, Santangelo, Steven wrote:
>Gentlemen,
>
>Thanks for your responses. I guess what I'm missing here is not being
>= able to see the timing margin issues. I've run many simulations of
>the = series-only case in the past and have recently started running
>the =
>series+parallel(S+P) cases. With an etch length of about 2.75" to the
>series+=
>SODIMM and at speeds up to 200MHz (400Mbps), I don't really see any =
>differences (timing wise) that would lead me to the S+P solution. At =
>200MHz, am I still too slow (not me, the circuit) to have to worry
>about = this or am I just looking at it wrong?=20
>
>In response to one of the comments, I effectively do have series terms
>= on both ends of the DQ and DQS lines since I have an on-board series
>= term along with the 22ohm series term on the SODIMM itself.
>
>Thanks again for your help.
>
>Steve
>
>
>
>
>-----Original Message-----
>From: Dan Bostan [mailto:dbostan@xxxxxxxxx]
>Sent: Friday, March 25, 2005 2:07 PM
>To: scott@xxxxxxxxxxxxx; Santangelo, Steven
>Cc: si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: DDR Termination
>
>
> From my experience, the parrallel termination can be eliminated, but
>only after reducing the length of traces and extensive simulations to
>make sure SI and timing are OK.
>As Scott said, the timing margins are smaller without the VTT parallel
>terminations.
>/dan
>
>--- Scott McMorrow <scott@xxxxxxxxxxxxx> wrote:
> > Steven
> >=20
> > The answer is: "Yes, you should be concerned."
> >=20
> > The primary reason for the parallel termination to
> > Vdd/2 is to center=20
> > the switching around Vref. At low speeds this is not critical. But
> >at=20 high speed, intersymbol interference (ISI) and pattern run
> >lengths of=20 all zeros and all ones will eat your timing margin
> >alive.
> >=20
> > There are two reasons for series termination. The first reason is
> >to=20 provide a better impedance match for the drivers.=20 The
> >second reason to=20 to provide resistive losses to de-Q resonances
> >in the channel. DDR even=20 with series and parallel termination
> >is not a well damped system. At=20 higher frequencies the channel
> >resonances will kill you.
> >=20
> >=20
> > best regards,
> >=20
> > scott
> >=20
> > Scott McMorrow
> > Teraspeed Consulting Group LLC
> > 121 North River Drive
> > Narragansett, RI 02882
> > (401) 284-1827 Business
> > (401) 284-1840 Fax
> >=20
> > http://www.teraspeed.com
> >=20
> > Teraspeed=AE is the registered service mark of Teraspeed Consulting
> >Group LLC =20 =20 =20 Santangelo, Steven wrote:
> >=20
> > >Hi,
> > >
> > >I'm looking at a DDR interface which consists of a
> > controller and a =3D
> > >single SODIMM module. In the past we've
> > successfully simulated, built =3D
> > >and tested this interface using only series
> > terminations but have always =3D
> > >run it fairly slow, 100MHz or 133MHz. As we crank
> > up the clock on =3D
> > >future designs I'm starting to wonder if we should
> > switch to the more =3D
> > >standard series+parallel termination scheme. Aside
> > from the increased =3D
> > >over and undershoot and any resulting EMI issues, I
> > don't see a big =3D
> > >difference between the 2 approaches. If anything,
> > the series only =3D
> > >approach appears to give me better noise margin due
> > to the increased =3D
> > >swing. Should I be concerned about using the
> > series termination only =3D
> > >approach when running at higher speeds, say 166MHz
> > or 200MHz? What =3D
> > >areas should I be concerned about?
> > >
> > >Thanks
> > >
> > >Steve
> > > =3D20
> >
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