[SI-LIST] Re: Query CMOS FPGA interface
- From: "Michael P. Busse" <mbusse@xxxxxxxxxx>
- To: <ha324005@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 5 Feb 2005 13:59:48 -0500
I am extremely frustrated by these emails while in India and China I
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to doing just what you are doing to me fill your email boxes up with "junk"
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this is pure nonsense - How the hell do I get out of here - don't send me
the unsubscribe because it does not work. Send me a name or phone number or
something that gets me to a real person to get out of this. I do not know
how many other people this is happening too but it has to be extremely
damaging to your organization. Please help me I have tried the nice ways to
get out and they don't work.
Thank you.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Himanshu Arora
Sent: Saturday, February 05, 2005 9:20 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Query CMOS FPGA interface
Hello,
I need to take output from IC and interface it with an
FPGA and the question pertians to that.
I have 1.8V rail-to-rail output from CMOS IC. It is a
80MHz signal, duty cycle atleast 50%, rise time around
1ns. The output driver in IC was designed assuming
15pF cap load (to take into account the package
capacitance, pcb track capacitance and the capaciatnce
due to FPGA package). This output becomes clock signal
for my FPGA.
I made a model of the package assuming about 5nH
bondwire inductance and 2nH package lead inductance
(for an SOICE type package). on using this lumpled RLC
model of package in HSpice simulations I see a lot of
ringing in the output of the driver.
Someone suggested me amkor MLF package with package
inductance of about 2nH...
I am wondering is FPGAs come in some similar kind of
packages and if so how complicated this problem is of
interfacing a CMOS rail-to-rail output with 1ns rise
and fall time with an FPGA which can take 1.8V CMOS
inputs? Bascially I am looking for the right package.
Thanks for your help.
Sincerely
Himanshu Arora
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