[SI-LIST] QDRII clock design
- From: Jean_Pierre.Bouthemy@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 13 Nov 2003 11:37:50 +0100
Hi SI Experts,
Just a question:
Do you think that the following clock signals K/KN, C/CN (from FPGA to
QDRII) and CQ/CQN (from QDRII to FPGA) should be considered as differential
signals, with equal length in order to minimize skew, and thus routed as
differential signals with coupling (risk of crosstalk?).
Any comment will be welcome.
Thank you for your help.
Jean-Pierre.
--------------------------------------------------------------------------
Jean-Pierre BOUTHEMY
Hardware Design Engineer
ALCATEL - Mobile Networking Division (MCG)
Mobile Core R&D
+33 (0)2 99 26 08 18
mailto:jean_pierre.bouthemy@xxxxxxxxxx
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