[SI-LIST] Re: Power/ground BGA assignment in package
- From: Jai Shanker <jswarrier@xxxxxxxxx>
- To: Ambr Amit <ambr_amit@xxxxxxxxx>
- Date: Wed, 2 Jul 2008 00:10:49 -0700 (PDT)
Hi Amit,
Looked like this didnt get any response on-list, maybe you got some help
directly. We havent directly done SI for chips but have designed with boards
DDR-2 (800) and serdes upto 10Gb. devices have mostly had central GND and VDD.
Things have worked.
1. We got some SI work done on the memory side and it didnt predict, and we
didnt observe any significant problems. Of course you are at higher speeds. We
had chips with IO VDDs of the DRAM placed between the exact chip centre and the
IOs themselves.
2. Maybe you can go for the scattered VDD/GNDs like the "sparse Chevron"
clusters in Virtex5.
3. With serdeses place their VDD and VSS rails close to their block locations
and their IO, and all these at the peripheries of your IC. Your exits for the
high speed routes are not blocked and your return paths are also OK.
Good luck with your chip.
rgds,
Jai
--- On Mon, 6/23/08, Ambr Amit <ambr_amit@xxxxxxxxx> wrote:
> From: Ambr Amit <ambr_amit@xxxxxxxxx>
> Subject: [SI-LIST] Re: Power/ground BGA assignment in package
> To: si-list@xxxxxxxxxxxxx
> Date: Monday, June 23, 2008, 11:27 AM
> Resending with subject added.
>
>
> Thanks and regards
>
> Amit
>
> --- On Mon, 6/23/08, Ambr Amit <ambr_amit@xxxxxxxxx>
> wrote:
> From: Ambr Amit <ambr_amit@xxxxxxxxx>
> Subject:
> To: si-list@xxxxxxxxxxxxx
> Date: Monday, June 23, 2008, 7:31 PM
>
> Hi,
>
>
> I'm working on a 6-layer flipchip package design
> with following stackup:
>
>
>
>
>
> VSS
>
>
> signal
>
>
> VDD
>
>
> VSS
>
>
> VDD
>
>
> Balls
>
>
>
>
>
> This package gets used on a 4-layer board with
> stackup of
>
>
>
>
>
> signal
>
>
> VSS
>
>
> VDD
>
>
> signal
>
>
>
>
>
> The design supports high speed interfaces like
> DDR3-1600 & multiple Serdes (upto 5Gbps). While doing
> ball
> assignment I'm proposing to place power/ground
> (VDD/VSS) balls in the
> perimeter of package (to get better return paths for high
> speed
> signals). But based on the board routing this is turning
> out to be bad
> idea because it blocks lot of signal routes and proposal is
> to move all
> the power/ground (VDD/VSS) inside towards the centre of the
> package.
> I'm not comfortable with this because
>
>
>
>
>
> - this will affect the return path
>
>
> - it results in current crowding in the central area where
> lot of VDD/VSS balls are places
>
>
> - and ineffective use of package internal planes
>
>
>
>
>
> This can result in SI issues. But sadly I do
> not have any data which can support that moving all the
> VDD/VSS towards
> centre will result in SI issues. One part is doing
> simulation to see
> the impact of bad return path, which I'm working on.
> But if someone in
> SI-list has already done study on this scenario, I would
> appreciate
> their opinions and data on this subject.
>
>
>
>
>
> Thanks and regards
>
>
> Amit
>
>
>
>
>
>
>
>
>
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