[SI-LIST] Re: Power/ground BGA assignment in package
- From: "Raymond Y. Chen" <chen@xxxxxxxxxxx>
- To: "'Ambr Amit'" <ambr_amit@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 27 Jun 2008 11:08:12 -0700
Amit,
This paper "Effects of Power/Ground Via Distribution on the Power/Ground
Performance of C4/BGA Packages" is a quick study on the core power delivery
system impedance, inductance and resonance, by comparing central,
peripheral, and other P/G via distribution patterns. Seems like close to
what you are looking for. It can be found here: paper 12,
http://www.sigrity.com/success/techpapers/support_tech_doc.htm. This paper
did not study the signal, power/ground return issue, and since it was a
paper 10 years ago, there must be more up to date studies out there.
This paper "Power Delivery Modeling and Design Methodology for a
Programmable Logic Device Package" is a related one on package layer count,
how via pattern/location can severely cause plane starvation (current
crowding) from IR drop and AC noise point of view. It can be found here:
paper 25, http://www.sigrity.com/success/cus_doc.htm. I am sure others on
this forum can give you more public references.
Raymond Y. Chen
Sigrity, Inc.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Ambr Amit
Sent: Monday, June 23, 2008 8:27 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power/ground BGA assignment in package
Resending with subject added.
Thanks and regards
Amit
--- On Mon, 6/23/08, Ambr Amit <ambr_amit@xxxxxxxxx> wrote:
From: Ambr Amit <ambr_amit@xxxxxxxxx>
Subject:
To: si-list@xxxxxxxxxxxxx
Date: Monday, June 23, 2008, 7:31 PM
Hi,
牋?I'm working on a 6-layer flipchip package design with following stackup:
VSS
signal
VDD
VSS
VDD
Balls
牋?This package gets used on a 4-layer board with stackup of
signal
VSS
VDD
signal
牋?The design supports high speed interfaces like DDR3-1600 & multiple
Serdes (upto 5Gbps). While doing ball assignment I'm proposing to place
power/ground (VDD/VSS) balls in the perimeter of package (to get better
return paths for high speed signals). But based on the board routing this is
turning out to be bad idea because it blocks lot of signal routes and
proposal is to move all the power/ground (VDD/VSS) inside towards the centre
of the package.
I'm not comfortable with this because
- this will affect the return path
- it results in current crowding in the central area where lot of VDD/VSS
balls are places
- and ineffective use of package internal planes
牋牋 This can result in SI issues. But sadly I do not have any data which
can support that moving all the VDD/VSS towards centre will result in SI
issues. One part is doing simulation to see the impact of bad return path,
which I'm working on. But if someone in SI-list has already done study on
this scenario, I would appreciate their opinions and data on this subject.
Thanks and regards
Amit
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