[SI-LIST] Re: Power Supply Distribution/Filtering/DecouplingGuide
- From: Zhangkun <zhang_kun@xxxxxxxxxx>
- To: scott@xxxxxxxxxxxxx, weirsp@xxxxxxxxxx
- Date: Thu, 08 Jan 2004 20:06:52 +0800
Dear Scott:
I have read you mail. There are a lot of good questions about power integrity
at PCB level. The following is my comment.
In the DesignCon2004, we (Cadence and Huawei) will propose one paper about the
effect of antipad and via on power integrity at PCB level. According to our
experience, there is no serious effect when there are a lot of caps on the
board.
In the other hand, there is important relationship between EMI and PI at PCB
level. Lowering the power ground noise not only could provide silent power
supply to IC, but also could reduce the EMI.
About the simulation and measurement of power integrity, I think there could be
great result.
Best Regards
Zhangkun
2004.1.8
----- Original Message -----
From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
To: <weirsp@xxxxxxxxxx>
Cc: <james.f.peterson@xxxxxxxxxxxxx>; <mark.alexander@xxxxxxxxxx>;
<si-list@xxxxxxxxxxxxx>
Sent: Thursday, January 08, 2004 3:38 AM
Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling Guide
> All,
> I love power distribution and decoupling discussions, because the
> problem is much more complex than anyone wants to admit. We can easily
> analyze planes quite accurately, as long as there are no holes, splits
> ... etc. but as soon as we include real antipads, real splits, and real
> reliefs, the electromagnetic modeling problem is a real bear. In
> itself this is not a trivial problem. Compound that with the fact that
> dielectric material properties for FR4 substrates are not that uniform
> and you end up with a pretty interesting set of extractions/simulations
> just to characterize the behavior of power distribution planes. Add in
> vias and antipads and you have a pretty tough problem.
>
> The Cadence/Sun power plane modeling and simulation solution does not
> take into account antipads and via modeling at all. This solution
> assumes that the model for breakout vias and antipads have been included
> in the model for the capacitors. The Sigrity Speed2000/PowerSI solution
> does provide a good approximate model for vias and antipads, but suffers
> from mesh size issues on large boards . In order to resolve return path
> mutual inductance issues between vias on a real board, you need a mesh
> that is small enough to resolve each via individually. For large
> boards, this means that the mesh has to be extremely large, requiring
> extremely high memory usage and run time. The Cadence/Sun solution does
> not even attempt to model via mutual inductance, and assumes that each
> component exists independently of all others, and that the power/ground
> mutuals have been modeled correctly for each device.
>
> Now, with some reasonable assumptions one can use a 3D solver like CST
> Microwave or HFSS to model capacitor mounting vias. And with some good
> measurements, one can then correlate and tweek the results to a high
> degree of accuracy. The assumption with this method is that there are
> no other near-field interactions between capacitor mounting vias and
> other vias on the board. Every one of these interactions will cause
> mutual inductance (and therefore loop inductance) to change, causing
> shifts in SRF and anti-resonance patterns in any area of a board. A
> reasonable solution might be to come up with a nominal mounted model for
> a capacitor, and then perform Monte Carlo or DOE simulations across an
> entire board. An interesting proposition in numerical simulation.
>
> To recap so far:
>
> * Planes on real boards a not simple to model
> * The Cadence/Sun approach idealizes the planes, excludes via
> interactions, antipads and splits.
> * The Sigrity approach models the planes, vias, antipads and splits
> in a more correct fashion, but suffers from mesh size problems,
> memory allocation and simulator performance problems for large
> boards with many planes and vias.
> * Via models are extremely sensitive to near field interactions with
> other vias, which cause shifts in mutual inductance values, and
> shifts in the actual return paths.
> * A "one mounted capacitor model covers all" approach suffers from
> inaccuracies in the modeled mutuals, and will result in shifts in
> the SRF and anti-resonance patterns.
>
> So, assuming that all of these things can be modeled and simulated in a
> reasonable fashion, the next question is "how do I model the only thing
> that really matters, the package and silicon?"
>
> If we have trouble trying to converge on a modeling and simulation
> methodology for planes, capacitors and vias, and we have issues even
> with creating a model for a capacitor with 2,4,6, 9 vias, imagine the
> problems we might have with the power delivery model for the package and
> device. Imagine trying to model a 1 mm pitch BGA with 1152 balls and
> coming up with a model that is even close to correct. Imagine what
> might be happening inside of the package, where it looks like a miniture
> PCB with vias, planes and traces. As core frequencies for many devices
> are now 200 to 500 MHz range, a lumped modeling approach is no long
> quite sufficient. For I/O power modeling, we are now seeing GHz and
> greater busses with risetimes in the sub 150 ps range. The package is
> no longer just a bunch of lumped inductors attaching the silicon to the
> PCB. It is now a very complex non-ideal transmission line and parallel
> plate mode structure that has all sorts of interesting resonance patterns.
>
> Now combine the silicon model to the package model to the BGA via
> breakout model to the PCB plane model (with antipads and vias) to the
> capacitor model .... and things get quite interesting. Oh, and what
> happens when you put more than one silicon device on a board, and
> another and another ... how do all these "things" interact?
>
> Oh, and just how much capacitance is on that silly little silicon die,
> and what exactly is the switching profile of the device? I've not yet
> seen any published data that is better than a 1st order approximation.
>
> Now, there is no doubt that if we are going to decouple a board with
> capacitors that lower mounted inductance is a good thing. The question
> I would pose is are we fighting over nits, when the real question is
> what difference does it really make at the silicon? And if the silicon
> is the important thing in this whole power delivery modeling and
> simulation exercise, then why aren't we talking about the modeling of
> silicon and packages first? And why are those at the semiconductor
> houses silent when it comes to this part of the problem. They are the
> only ones who have access to any of the data needed to actually perform
> power distribution simulations for core or I/O power. They are the only
> ones who have modeled their packages and have access to them. (Oh, and
> please don't tell me that these companies provide models of their
> packages. They do, but I have yet to see one that is accurate enough
> for robust power delivery simulations above 100 MHz. And most still do
> not provide any data on the switching current profile of the core, a
> good lossy model for the excess capacitance of the core, or a good lossy
> model of the excess capacitance of the I/O ring, or a good high
> frequency lossy model for the power distribution network on the package.
>
> If you think that SRF and anti-resonance peaking is limited to just the
> capacitors on the plane, then you might want to look at this again and
> think about the many vias and balls in parallel which connect the core
> of a die almost directly to the planes, and the fragmented structure
> often used to connect the I/O power ring of a piece of silicon through
> the package, balls and vias to a PCB.
>
> After performing this exercise, one might want to wonder whether
> capacitors are that important after all in the grand scheme of things.
> And once everything is said and done, how might I actually find the
> "worst case" noise problem in a complete system?
>
>
> best regards,
>
> scott
>
> --
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
>
>
>
>
> steve weir wrote:
>
> >Jim,
> >
> >The "myth" refers to the acceptability of spacing by such a wide
> >amount. Mark is clearly aware of antiresonance, and did a very reasonable
> >job of discussing it in his application note. For like mounted
> >inductances, a 10:1 spread in capacitance yields a 3:1 spread in SRF which
> >is wide enough to cause quite a bit of anti-resonant peaking. Mileage
> >varies depending on the via attachments and distance to the planes, as well
> >as with capacitor packages.
> >
> >To simplify a little bit, if the mounting inductance dominates, then the
> >total inductance won't change much even with package reduction, and the
> >SRF's will in-fact space about sqrt( C ratio ), and the anti-resonant peaks
> >will space about C_ratio ^ 0.25. If the mounted inductance is not
> >dominant, then the SRF's, and anti-resonant peaks will spread further. The
> >further they spread, the higher they are.
> >
> >There has been a lot of good work, led by the folks at SUN in the late
> >1990's showing these effects.
> >
> >There is also a devil with not using a spread in capacitor values, the
> >technique advocated by Henry Ott, and Howard Johnson, and that is the
> >anti-resonant peaking that occurs against the planes. An ideal solution is
> >to use capacitors with a low mounted Q. AVX has some, and a number of the
> >X2Y caps exhibit comparatively low Q's. The alternative is to reproduce
> >bass-reflex loudspeaker design using techniques outlined by SUN, and now
> >embodied in both Cadence, and UltraCAD's tools.
> >
> >Regards,
> >
> >Steve.
> >At 06:16 AM 1/7/2004 -0700, Peterson, James F (FL51) wrote:
> >
> >
> >>Mark -
> >>
> >>regarding steve's comment and your response :
> >>
> >>
> >>>>Capacitors values spaced over decades is largely a myth that has been
> >>>>debunked.
> >>>>
> >>>>
> >>>By who? Please refer me to relevant papers.
> >>>
> >>>
> >>"largely a myth" might be overstating it, but I've seen a paper that does
> >>state this position - written by Henry Ott (I believe it was in the PCD
> >>mag). His position is that the benefit of mixing ceramic values is lost
> >>because of the poles it introduces (caused by ESL of the one cap and the C
> >>of the other). I don't totally agree with it, but there is some merit to
> >>this position. like anything in this business, it needs to be analyzed
> >>(modeled and simulated) sufficiently.
> >>
> >>regards,
> >>jim peterson
> >>Honeywell
> >>
> >>-----Original Message-----
> >>From: Mark Alexander [mailto:mark.alexander@xxxxxxxxxx]
> >>Sent: Monday, January 05, 2004 8:44 PM
> >>To: steve weir
> >>Cc: Mark Alexander; Tegan.Campbell@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >>Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decoupling
> >>Guide
> >>
> >>
> >>Steve,
> >>Thank you for the comments -- this sort of criticism is always helpful.
> >>
> >>In defense of the strategies we advocate in this appnote, there are many
> >>ways to skin a cat. I'm presenting methods that we have seen repeatedly
> >>to work well for FPGA designs. The aim was not to write a flawless
> >>treatise on the art -- it was to put forth a guide that any PCB designer
> >>can use with success.
> >>
> >>The items you've listed below are valid points. I could go through them
> >>and tell you why I decided to present the information that way, but
> >>that's not the point. Many simplifications were made in order to get
> >>the basic points across. I encourage people to take this appnote for
> >>what it's worth -- a fairly comprehensive set of guidelines that we know
> >>will work with our devices.
> >>
> >>I will take into consideration what you've said below, in particular the
> >>points on X2Y caps that we haven't investigated in detail yet. I'll
> >>also put some notes inline below.
> >>
> >>Regards,
> >>mark
> >>
> >>
> >>steve weir wrote:
> >>
> >>
> >>
> >>>Mark,
> >>>
> >>>I have a few other comments on that appnote:
> >>>
> >>>Figure 6 shows the induction loop only including the capacitor down to
> >>>the power layer. This needs to be changed to show the whole loop of
> >>>interest is effectively from the capacitor to the far plane. The
> >>>interplane capacitance density is nothing like that of the decoupling
> >>>cap and cannot support the field.
> >>>
> >>>
> >>Point taken that the loop shown in figure 6 is not the whole story.
> >>However as to the capacitance density of BC being able to support the
> >>field, I think the jury is out on this point.
> >>
> >>
> >>
> >>>I am not happy with the characterization of capacitor effective
> >>>frequency.
> >>>
> >>>
> >>I am.
> >>
> >>
> >>
> >>>I think that this is where the note is the weakest as I think it lends
> >>>itself to the idea that a broad range of closely spaced capacitor
> >>>values must be used. That is one strategy that can work and is
> >>>promoted by both UltraCAD, and the work done by SUN. But, it is not
> >>>the only solution.
> >>>
> >>>
> >>Agreed. As for now, it's a valid solution and we still stand by it.
> >>Ceramic caps lend themselves to decoupling. They also have fairly
> >>high-Q, which can bite you if you're not careful. This is why we
> >>emphasized the simple first-order stuff.
> >>
> >>
> >>
> >>>As traditional geometry capacitors become less relevant for
> >>>decoupling, it will become less applicable.
> >>>
> >>>
> >>True, but we're not there yet. There's plenty of mileage left in
> >>traditional discretes.
> >>
> >>
> >>
> >>>You should update your description of the effective resonant frequency
> >>>to include ESR. With many capacitors the Q is so high that ESR does
> >>>not shift the damped natural frequency significantly. But, with
> >>>others like X2Ys, it does.
> >>>
> >>>Rather than using frequency as the basis for capacitor placement, I
> >>>suggest changing to time domain current demand and inductance.
> >>>
> >>>
> >>Agreed. However it's tough to justify this level of analysis in an
> >>appnote of this scope.
> >>
> >>
> >>
> >>>It is readily shown how little even a lot of BC supports large
> >>>switching currents.
> >>>
> >>>
> >>Where? It depends which analysis you look at and the approximations you
> >>assume. I'll bet that on this list we could find equal numbers of
> >>successful designers in each camp.
> >>
> >>
> >>
> >>>While I liked your discussion of decoupling placement radius in
> >>>general, I think your propagation constants are too fast leading to
> >>>liberal radii. Power planes behave as striplines and will be more
> >>>like 180 to 220 ps/in than 130 ps /in of a surface microstrip.
> >>>
> >>>
> >>See John Zasio's discussion in Right The First Time. What do you think
> >>of it?
> >>
> >>
> >>
> >>>Capacitors values spaced over decades is largely a myth that has been
> >>>debunked.
> >>>
> >>>
> >>By who? Please refer me to relevant papers.
> >>
> >>
> >>
> >>>Mounted SRF's vary by about 3:1 with such an arrangement, leading to
> >>>significant antiresonance at about 1.7X the lower SRF.
> >>>
> >>>
> >>Which is why we recommend the use of multiple values of these high-Q
> >>elements (ceramic caps).
> >>
> >>
> >>
> >>>UltraCAD and SUN have both shown that spacing values by no more than
> >>>2:1 yields a PDS impedance using far fewer parts than spacing on
> >>>decades.
> >>>
> >>>
> >>?? I'm missing something... doesn't that mean their networks would have
> >>more values, not less?
> >>
> >>
> >>
> >>>I am doing some work now on further reducing this with X2Y caps. My
> >>>personal view on decoupling HF is that the first approximation is from
> >>>raw vias. The number of capacitors falls out from the number of vias,
> >>>and the type of capacitor technology selected.
> >>>
> >>>
> >>I agree with you here. I think this is where it's going. Again, we'll
> >>be a step or two behind in what we publish as an appnote. We can't
> >>afford to publically recommend methods that aren't fully understood.
> >>
> >>
> >>
> >>>
> >>>Regards,
> >>>
> >>>
> >>>Steve.
> >>>
> >>>
> >>>
> >>>
> >>>
> >>>Steve
> >>>At 05:28 PM 1/5/2004 -0700, Mark Alexander wrote:
> >>>
> >>>
> >>>
> >>>>Steve, Tegan,
> >>>>
> >>>>That appnote is one of mine, and you're correct -- these are
> >>>>representative numbers, not hard values. When this was written 2
> >>>>years ago, very few people were making measurements with accuracy
> >>>>that could distinguish between a 500pH mouting and a 650pH mounting.
> >>>>That's a bad excuse -- now that this information is more commonplace,
> >>>>it looks like I've got some updating to do, even if only to put some
> >>>>bounds on the accuracy of the numbers presented.
> >>>>
> >>>>John Zasio's section of Lee's book is a good place to go for numbers,
> >>>>as are the papers on Istvan Novak's webpage. In particular, see the
> >>>>DesignCon 2003 TecForum paper and the EPEP 2003 paper.
> >>>>
> >>>>-mark
> >>>>
> >>>>
> >>>>
> >>>>steve weir wrote:
> >>>>
> >>>>
> >>>>
> >>>>>Tegan, the numbers in that application note are
> >>>>>representative, and not
> >>>>>hard values. The smaller values in-particular depend greatly on the
> >>>>>distance to the planes. I think they are a little optimistic with
> >>>>>their
> >>>>>shown 600 and 500 pH configurations. My experience is that those
> >>>>>would run
> >>>>>more like 800pH and 650pH respectively. But, again, that depends on
> >>>>>the
> >>>>>height above the planes.
> >>>>>
> >>>>>I also would not use their configuration (d). For a four via
> >>>>>connection,
> >>>>>placing the vias on either side of the long axis of the pad results in
> >>>>>lower inductance than outboard of the long axis of a normal geometry
> >>>>>capacitor. That doesn't matter too much when using a crummy
> >>>>>capacitor with
> >>>>>800-900nH of package inductance, but it can make a big difference if you
> >>>>>use reverse geometry, or X2Y caps.
> >>>>>
> >>>>>0603's 750pH package
> >>>>>0306's 200pH package
> >>>>>0603 X2Y 120pH package
> >>>>>
> >>>>>We can range from single via mounts of 800pH to three via mounts of 300pH
> >>>>>
> >>>>>
> >>>>>to get resulting inductances of:
> >>>>>
> >>>>>420pH X2Y three via to 1550pH 0603 with single vias. In either
> >>>>>case, to
> >>>>>get to a given target impedance we are driven to drill a commensurate
> >>>>>number of via holes, and then add caps. The worst choice is
> >>>>>traditional
> >>>>>caps, where we need to drill about 25% more holes and need almost 4X as
> >>>>>many capacitors total versus using X2Ys. Reverse geometry caps can
> >>>>>just
> >>>>>about get away with a like number of holes as X2Ys, but need about 25%
> >>>>>more
> >>>>>caps than X2Ys due to the higher package inductance.
> >>>>>
> >>>>>Condemned was only a reference to the effort needed to find and collect
> >>>>>the
> >>>>>papers. It would be great if there was a single comprehensive
> >>>>>reference
> >>>>>for this subject, but I don't know of one.
> >>>>>
> >>>>>Steve.
> >>>>>At 03:27 PM 1/5/2004 -0700, Tegan Campbell wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>
> >>>>>>All,
> >>>>>>There is a Xilinx app note on their site(Xapp 623) that they talk about
> >>>>>>different mounting inductances of capacitors but give no source for
> >>>>>>their
> >>>>>>information. I noticed that Lee Ritchey said in an earlier email he
> >>>>>>had
> >>>>>>data to back up modeled inductances of different mounting structures.
> >>>>>>Does anyone with the knowledge want to take the time to look at the
> >>>>>>paper(figure 5) and provide data that agrees or disagrees with their
> >>>>>>assumptions?
> >>>>>>
> >>>>>>And Steve, "condemned" might be a bad choice of words in the
> >>>>>>paragraph
> >>>>>>below. I found some VERY useful information and perspectives in
> >>>>>>those
> >>>>>>papers.
> >>>>>>
> >>>>>>Tegan
> >>>>>>
> >>>>>>
> >>>>>>Hassan,
> >>>>>>
> >>>>>>I don't know of one place you are going to find all of that. There
> >>>>>>are a
> >>>>>>series of worthwhile chapters in Lee's book: "Right the
> >>>>>>First
> >>>>>>Time". There is also some coverage in Dr. Johnson's
> >>>>>>book: "High Speed
> >>>>>>Digital Design", and Hall's book as well. Beyond those titles,
> >>>>>>I think you
> >>>>>>are condemned to plucking out papers such as many written by the folks
> >>>>>>at
> >>>>>>SUN, and others.
> >>>>>>
> >>>>>>Steve.
> >>>>>>At 04:52 PM 1/5/2004 -0500, Hassan O. Ali wrote:
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>
> >>>>>>>Could anyone recommend a definitive design guide for board-level
> >>>>>>>power
> >>>>>>>distribution,
> >>>>>>>filtering, and decoupling suitable for PCB's with multi-voltage,
> >>>>>>>multi-gigabit, mixed-
> >>>>>>>signal devices?
> >>>>>>>
> >>>>>>>Thanks.
> >>>>>>>
> >>>>>>>Hassan.
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>>
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