while the si-list is talking about power distribution... I have a 2" by 1" PCB that contains one IC that drives a whole set of series terminated transmission lines. It always clocks data at 200MHz. Due to the impedance of the transmission lines, the current required by the driver IC requires there to be about 10-14 GND/POWER/GND layers, along with low inductance IDC caps (for a flat impedance out to 1GHz). Buried Capacitance may need to be considered, however it has been suggested that it be avoided if possible. My basic problem is that the housing limits the size of the PCB, which restricts the power plane area. Is there an alternative approach that I ought to consider, or have I approached it the only practical way. Cheers, Peter Baxter ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu