[SI-LIST] Re: Power Integrity Question
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Jerry Johnson <gerald.johnson@xxxxxxxxxxxx>
- Date: Thu, 06 Nov 2008 09:09:52 -0500
Jerry,
Yes, the part uses the standard X2Y footprint...
Regards,
Istvan
Jerry Johnson wrote:
> You can get them from Digi-Key overnight.
> They seem to work great, but we had to change our PCB
> footprint. The dimensional specifications on the width
> and placement of the side contacts are really loose, so
> you need narrow pads on the end caps to avoid potential
> shorts. That could open the door to tombstoning during
> assembly. Sure wish those dimensional specs were tighter.
>
> Jerry
>
> steve weir wrote: They're in their catalog. I haven't seen any though. Steve
> Peterson, James F (EHCOE) wrote: (follow-up to Steve's comments on Q)
> Whatever happened to the technique that TDK came up with a couple years back
> where they were purposely increasing a capacitor's ESR to reduce Q (and thus
> the large peaks mentioned in this thread)? I remember seeing it a few
> DesignCons ago - it seemed like such a great idea... Jim. -----Original
> Message----- From: si-list-bounce@xxxxxxxxxxxxx[1]
> [mailto:si-list-bounce@xxxxxxxxxxxxx[2]] On Behalf Of steve weir Sent:
> Thursday, November 06, 2008 8:07 AM To: Avtaar Singh Cc:
> si-list@xxxxxxxxxxxxx[3] Subject: [SI-LIST] Re: Power Integrity Question The
> simulators are reporting correctly. Your understanding of physics theory (
> actually Calculus ) is incorrect. A convenient way to think about the
> impedance anywhere is as a result of the characteristic impedance and the Q.
> In the original case, the impedance significantly away from the original
> poleapproximates the characteristic impedance. At each of the two peaks,
> whenthe impedance is reactive, Q >1, and the peak impedance is substantially
> greater than the characteristic impedance. Therefore if you've got peaks at
> all the impedance will always be above the original curve surrounding each
> one. Steve. Avtaar Singh wrote: Dear All: I have a very basic Power
> Integrityquestion. Lets say a Power Delivery Network (PDN) has an impedance
> peak at 100MHz. I add a capacitor that dips the impedance exactly at 100
> MHz,and creates 2 smaller peaks at, lets say, 20 MHz and 250 MHz. According
> to the theories of Physics, these peaks should have their impedance value
> little bit lesser than the impedance value of the PDN, at those 2 frequency
> points, before this capacitor was added. But we do not always see that in
> simulation tools. Sometimes we see that the 2 peaks that are formed have
> higher impedance than the impedance that existed at those frequency points
> before this last capacitor was added. This seems weird to me, because even
> though the ESR of the caps should decide how sharp or blunt the Z peaks are,
> but an added Z in parallel should always mean lesser impedance rather than
> more impedance. Can someone please explain this paradox? Thanks for the kind
> guidance. Regards, Avtaar Singh
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