[SI-LIST] Re: Planar DDR and LVTTL I/O
- From: "Ravinder Ajmani" <ajmani@xxxxxxxxxx>
- To: kacief@xxxxxxxxxxxxx
- Date: Tue, 1 Oct 2002 19:10:32 -0700
Hi Jim,
You have raised some very interesting and important points. Will you
please elaborate why does one need Vref for the input buffers, and what is
the duty cycle variation of output of the input buffers, and how does it
impact operation over 100 MHz. When you talk of skew between DQS and Data
being intolerable to ASIC, does it have any relation to CMOS buffers, or
will this be the case for using single DQS with a wide memory bus. I have
seen very wide variations between Data and DQS timing for different memory
vendors (some put out Data before DQS, and some after). What should be the
routing guidance for skew control.
I will very much appreciate your response.
Regards, Ravinder
PCB Development and Design Department
IBM Corporation
Email: ajmani@xxxxxxxxxx
***************************************************************************
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jim freeman
<kacief@xxxxxxxxx To:
robert.lindsell@xxxxxxxxxxxxxxxxxx
.com> cc: si-list@xxxxxxxxxxxxx
Sent by: Subject: [SI-LIST] Re: Planar
DDR and LVTTL I/O
si-list-bounce@fr
eelists.org
10/01/2002 11:12
AM
Please respond to
kacief
Hi Robert,
A vref for the input buffers may be essential. The duty cycle variation
for the output of the input buffer may be too great to run at greater than
100Mhz clock frequency. There are also duty cycle variations for the clock
driver that are quite stringent. I asume that your bus width is wide enough
to require more than one memory chip. If you are able to use only one
memory
chip, the skew between the dqs and the data may be intolerable for the ASIC
controller.
Thanks
Jim Freeman
Robert Lindsell wrote:
> Hello si-listers,
>
> Does anyone know if it's possible to use 2.5V LVTTL/LVCMOS buffers with
> a planar, point-to-point implementation of DDR (ie. no DIMMs, just one
> DDR chip and an ASIC controller)
>
> Our ASIC library vendor wants $50k for SSTL-2 buffers, which seems a bit
> extreme... but maybe it isn't????
>
> Any info and opinions welcome.
>
> Regards,
>
> Robert
>
> --
> Robert Lindsell, Principal Hardware Engineer
> Canon Information Systems Research Australia
> PO Box 313 NORTH RYDE NSW 2113
> mailto:robert.lindsell@xxxxxxxxxxxxxxxxxx
> Fax: +61-2-9805-2929 Phone: +61-2-9805-2876
>
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