[SI-LIST] Re: Planar DDR and LVTTL I/O
- From: jim freeman <kacief@xxxxxxxxxxxxx>
- To: robert.lindsell@xxxxxxxxxxxxxxxxxx
- Date: Tue, 01 Oct 2002 11:12:50 -0700
Hi Robert,
A vref for the input buffers may be essential. The duty cycle variation
for the output of the input buffer may be too great to run at greater than
100Mhz clock frequency. There are also duty cycle variations for the clock
driver that are quite stringent. I asume that your bus width is wide enough
to require more than one memory chip. If you are able to use only one memory
chip, the skew between the dqs and the data may be intolerable for the ASIC
controller.
Thanks
Jim Freeman
Robert Lindsell wrote:
> Hello si-listers,
>
> Does anyone know if it's possible to use 2.5V LVTTL/LVCMOS buffers with
> a planar, point-to-point implementation of DDR (ie. no DIMMs, just one
> DDR chip and an ASIC controller)
>
> Our ASIC library vendor wants $50k for SSTL-2 buffers, which seems a bit
> extreme... but maybe it isn't????
>
> Any info and opinions welcome.
>
> Regards,
>
> Robert
>
> --
> Robert Lindsell, Principal Hardware Engineer
> Canon Information Systems Research Australia
> PO Box 313 NORTH RYDE NSW 2113
> mailto:robert.lindsell@xxxxxxxxxxxxxxxxxx
> Fax: +61-2-9805-2929 Phone: +61-2-9805-2876
>
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