[SI-LIST] Re: Peak Distortion Analysis
- From: "Dmitriev-Zdorov, Vladimir" <vladimir_dmitriev-zdorov@xxxxxxxxxx>
- To: "Cheng, Chris" <chris.cheng@xxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 26 Feb 2013 18:02:11 +0000
Chris,
Thank you for the detailed observation: it defines many sensitive points in
SERDES analysis.
I share reasonable skepticism about fidelity of the PDA and statistical
analysis when applied to real life designs. This is also true for time domain
or bit by bit analysis, even if we assume it can work miraculously fast and
does not have a sample size problem limiting for the desired BER level.
Inaccuracies come from many sources, including channel characterization,
modeling of Tx and Rx signal processing in Spice, IBIS AMI or other
representations. Some of those we - EDA tool - can control (e.g. finding
accurate channel response) but some can't. We can only hope that the models we
get are somewhat close to reality and do best assuming it is true. In that
regard, we cannot overestimate an importance of correlation to measurements,
whenever possible.
> I do feel a hybrid approach of combining PDA with statistical analysis can be
> a good compromise.
Agree. But, I would even extend your proposal onto combining 3 methods: PDA,
statistical AND bit by bit analysis. By doing so we can - at least partially -
tackle the problems you mentioned: a need for end to end channel
characterization - not just the one at the Rx input, plus considering possible
Tx/Rx parameter adaptation, and back channel communication.
>My question is, how do you define your worst case pattern under the above
>system ? At the minimum the equalization is divided between the Tx FIR, Rx
>CTLE/VGA and Rx DFE. In our observation, at least the DFE is moving in time
>and does not stay constant. I've seen claims that even the CTLE is non linear
>and subject to large signal variation. How do we lock down the tap settings
>for the FIR, CTLE and DFE to generate the PDA worst case pattern ? To make
>things even more interesting, there are standards (such as 12G SAS) which
>allows back channel adjustment between the Tx and Rx.
Imagine a typical bit by bit analysis, which by way of Spice, behavioral, or
IBIS AMI models can include constant or adaptive CTLE, DFE and CDR effects so
that the waveform we get at the sample point somehow describes the combined
effect of those blocks. We know that probabilities of 1e-12 or below are
unreachable, but what if we include PDA and statistical into this flow? To do
that, we of course need to get the end to end link response, an equivalent edge
or impulse response dynamically. This is doable: EDA tool can control the
pattern it applies at Tx and gets the waveform from Rx (possibly, with the
synch times from its CDR). By having the two waveforms, there is a method we
use to extract an equivalent impulse or edge response - some type of
de-convolution. There is also a way to make it numerically well-defined. After
we get this equivalent response, we can pause bit by bit flow, to give way to
PDA and statistical analysis performed by EDA tool so that we get the LTI-wise
snapshot of Eye/BER giving us low probability estimates within the long non-LTI
development in bit by bit analysis, and possibly even in presence of
back-channel communication. Then, we should resume time domain analysis and
after a while produce another snapshot based on the newly extracted response.
Having them accumulated over a periods of simulation, we can hope to get a
better feeling of what we are dealing with. Ultimately, we build the combined
statistical picture from many of those partial characterizations.
Yes, the analogy with the elephant in the dark room applies well. Different
types of analyses give us different perspectives.
> Your worst case pattern may induce a dynamic adjustment of the equalizer
> settings that may results in a different worst case pattern.
In the above flow, the models do not feel that we do something behind their
backs. PDA & statistical analyses are used to repeatedly build statistical
EYE/BERs. Time domain development is needed to consider adaptation and other
non-LTI effects.
But, there is a choice flow that we implemented (presented at DesignCon couple
years ago). By making PDA from the snapshot response, we get the worst pattern
(with respect to Rx output) and then apply it immediately as an input to the
ongoing bit by bit analysis. This gives extra stress to the models and may
reveal some hidden corners. We call it stress mode simulation: it produces more
stressed eye/BER as compared to the bit by bit analysis with a 'regular' input.
Since PDA is combined with statistical, we have an estimate of where we are
with this PDA in terms of probability, and adjust the resulting BER accordingly.
How else we can combine the advantages of non-LTI compliant bit-by-bit
analysis, with an low probability insight provided by PDA and statistical?
Vladimir
-----Original Message-----
From: Cheng, Chris [mailto:chris.cheng@xxxxxx]
Sent: Monday, February 25, 2013 5:31 PM
To: Dmitriev-Zdorov, Vladimir; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Peak Distortion Analysis
Vladimir,
Great insights. And I would like to add the following observations.
I have search high and low (almost 14 years) for a real life case of
non-optical related BER 12 or 15 shipping product and even ask for one in
Si-list. So far there is no taker willing to tell me they are shipping a
product that takes an error every few hours or days. All the cases I've seen
are related to manufacturing defects or even alpha particle induced failures.
None can be traced back to "signal integrity" BER. I've always suspect BER
analysis is like the 3 sigma tester guard band we so often used in the last
century (80's and 90's) for timing analysis. Designers are simply uncomfortable
in shipping a design (no matter how thorough the analysis is) without some kind
of sandbagging. Tester guard band is the easy blame in the old days and now Rj
just carry the same burden. After all, you don't know what you don't know and
random is a pretty unknown thing to most people including myself. And the
cottage industry that generates around Rj analysis carries a life of its own.
I have accepted some form of statistical Rj is here to stay no matter how
difficult I found to have a real life product that exhibits this problem.
I do feel a hybrid approach of combining PDA with statistical analysis can be a
good compromise.
But I do feel it is harder and harder to define the two approaches.
Let's start with PDA.
I think the classical impulse channel response to worst case pattern is
probably over simplified the problem. Dual edge or even multi-edge worst case
pattern will probably be a better PDA for our current need. However, there is a
big issue I see in PDA for higher speed SerDes. Starting with speed as low as
6Gb/s and certainly above 10Gb/s, we observed a significant disconnect between
eye opening observed at the input of receiver (some form of probing) and
equalized output of receiver (through some margining tool in internal phase and
voltage). What I mean is the best eye opening observed at the receiver pin may
not be the best eye opening at the equalized receiver output. In fact, we've
seen cases of the best post equalized receiver eye comes from a totally closed
eye at the input pins. There are many reasons for this. Typical SerDes
designers assume certain channel loss to begin with their design, the CTLE or
DFE will default to a minimum peaking or post cursor tap equalization. If you
have a perfect eye opening at the receiver input pins, you may end up having an
over equalized eye that is worst than you expected. To complicate things
further, the CDR circuit may take a separate path of equalization with its own
peaking setting. Your CTLE and DFE may do its job and have the best eye opening
at the slicer, if your CDR have the wrong frequency peaking response (e.g. due
to high frequency ISI), you may still end up with a worst eye opening because
the CDR moves the sampling point to a phase you don't expect.
So what we are really going after is an end to end channel analysis where we
have to analyze signals from the input of the Tx to the output of the equalized
receiver at the slicer subjected to the sampling phase variation.
My question is, how do you define your worst case pattern under the above
system ? At the minimum the equalization is divided between the Tx FIR, Rx
CTLE/VGA and Rx DFE. In our observation, at least the DFE is moving in time and
does not stay constant. I've seen claims that even the CTLE is non linear and
subject to large signal variation. How do we lock down the tap settings for the
FIR, CTLE and DFE to generate the PDA worst case pattern ? To make things even
more interesting, there are standards (such as 12G SAS) which allows back
channel adjustment between the Tx and Rx. Your worst case pattern may induced a
dynamic adjustment of the equalizer settings that may results in a different
worst case pattern.
To flip the problem around to the statistical guys.
How does your LTI work if the tap setting is changing in time and pattern
dependent ? There are even claims that the jitter transfer characteristics is
linear only when your jitter amplitude is small compared to UI. What if you
have a closed eye as mentioned above where the jitter (deterministic or not)
dominates the overall eye opening ?
Given the above problems, I believe that best compromise will be to use your
PDA to converge to close to the worst case tap settings and then operate your
statistical analysis with those setting (I think some people call it state
space analysis).
A lot of AMI models claim they can do CDR or DFE modeling. But that may simply
be based on a impulse model generate state space tap setting that may or may
not be the worst case tap setting. Not to mention back channel adjustment.
I am not saying inheritably AMI models cannot support the hybrid approach. It's
just hard for that to happen in real life. Think in a real life SerDes model
generation. The SerDes designer most likely will never know the real life
channel application. He/She will designed it based on some ideal spec that
he/she assumes the SerDes will go into. The application engineer then take the
full circuit and abstract it to the best he/she knows. The CAD tool vendor will
try to anticipate what the SerDes looks like and come up with the template that
the model needs within the AMI framework. And the system design end user will
take a leap of faith that he/she may or may not even be able to validate in
real life. This is like the story with blind folded men in a room with an
elephant. One holds the tusk, the other holds the leg, another feels the ear
and yet another feels the belly..... I hope you catch what I am saying. I claim
it is always a leap of faith as it is close to impossible to really measure
what the slicer sees. Many silicon application engineer or CAD vendor claim
they are doing a good job until we sit down and review the real model and
compare that with real life measurement. Sometimes they just clamp up and claim
the model is proprietary even though they are not close to reality.
How many year since IBIS comes out with SSO models ? And how many IBIS models
actually got shipped by chip vendors that has SSO model included ?
I think there will be a lot of AMI SerDes models being released. How many of
them actually go beyond simple taps of FIR, linearized CTLE and simple pulse
deduced taps of DFE that can truly have variable hybrid timing domain and
statistical state space support will be interesting to see.
Finally, I don't claim I have the definitive solution for the above problems. I
am still a seeker and have an open mind for anyone who claim they have a
solution. Just prepare to show us data.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Company
+1 510 413 5977 / Tel
chris.cheng@xxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
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