[SI-LIST] Re: Parasitic capacitance of vias
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxx>
- To: <degers@xxxxxxxxxxxxxxxxxxxx>, <chris.mcgrath@xxxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Sep 2002 08:14:41 -0600
Here it is:
http://www.sigcon.com/pubs/news/viacapacitance.pdf
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Michael J. Degerstrom
Sent: Friday, September 13, 2002 7:36 AM
To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Parasitic capacitance of vias
Chris,
The formula provided by Johnson/Graham bounds the upper limit of the
capacitance by assuming the via is surrounded by a coaxial shield with a
diameter equal to the antipad diameter. My first guess would be that the
actual capacitance of the via is at least half the upper limit value. Dr.
Johnson posted a table with more accurate via capacitance estimates on his
website several months ago, but I was not able to find it.
Mike
On Thursday 12 September 2002 02:28 pm, chris.mcgrath@xxxxxxxx wrote:
> In the Johnson/Graham text (Section 7.2), it discusses parasitic
> capacitance being the result of several PCB parameters including the
> diameter of the via pad and the diameter of the clearance hole in the
> ground planes. However, there is a caveat that states that the equation
> "assumes there is a pad on every layer" and that if the designer omits
pads
> on layers not connected to traces (as we are doing), this should "slightly
> reduce the parasitic capacitance". Does anybody know by how much? In my
> case, the parasitic capacitance actually makes enough of a difference to
> warrant asking the question.
>
> Thanks,
> Chris
>
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