[SI-LIST] PECL to CMOS conversion
- From: Chris Landrum x311 <clandrum@xxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 6 Nov 2003 09:02:11 -0500
Anyone have a good method of converting a PECL signal into a 1.8V CMOS
signal. By "good signal", I mean one that has low jitter and is clean
looking.
Currently I have a 156MHz clock driver drving a PECL clock signal to a part
that has a single ended clock input (1.8V CMOS). I have terminated it as
per the following:
peclclk_n is terminated with 150 Ohm res to GND.
peclclk_p is AC coupled (100nF) and then terminated with a THEV
parallel circuit to 1.8V (to set the bias). The thev term
resistors are both 150 Ohm. This gives me a symmetrical
swing right at 0.9V.
The result is a very acceptable looking clock, but unfortunately, it appears
to have too much jitter for the receiving device. As an example, the stated
output jitter of the PECL buffer is
JITTERosc + 2ps = ~10ps (max).
I measure 25ps of cyc-cyc jitter on the input of the recieving device.
Doesn't quite add up.
Any thoughts?
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
