[SI-LIST] Re: PECL termination technique?

  • From: "john lipsius" <johnlipsius@xxxxxxxxx>
  • To: <hariharan@xxxxxxxxxxx>, "'SI-LIST'" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 16 Feb 2003 15:24:57 -0800

Hariharan,

I overlooked that the MC100 device is a 5V only chip.  So is the 
Cypress part.  Therefore, the Cyp appnote isn't applicable and 
you don't need to shift Vcm to a 3.3V receiver.  That is, the 
pullups to 5V shouldn't be used for that function.

However, the lack of dc pulldown to Vtt = Vcc-2 = 3V is still a question. 
The appnote circuit does provide this, so we know it's explicitly called 
for on the board, regardless of the receiver Vcc. 


-----------------------------------------------------------------

Separate issue:  I've further cleaned up the 5V to 5V termination 
details. 

Y-termination for differential PECL to PECL, 
with 5V as an example (driver and receiver) 

In the previous circuit I gave, as follows,

---Rs-------------------Vin (+)
                          |
                          R
                          |
gnd--220pF-- (Vtt) --- Rt ----gnd   
                          |                     
                          R            The 220pF cap is for further common mode 
filtering. 
                          |
---Rs-------------------Vin (-)


if Rs is used then the Ioh and Iol equations I gave must include 
it:

From dc mesh current analysis (Kirchoff's Voltage Law), 
Ioh = [(Rt/[R+Rs])*(Voh - Vol) + Voh] / ( [R+Rs] + 2Rt )  
Iol = [(Rt/[R+Rs])*(Vol - Voh) + Vol] / ( [R+Rs] + 2Rt )    
but these eq. aren't needed here.

Node currents, Kirchoff current law, is an easier method to get 
Rs, R, Rt  (with Rs included, as well):

Voh+Vol = Vtt(2+[(R+Rs)/Rt])
or
((Voh+Vol)/Vtt) - 2 = (R+Rs)/Rt        


Using Vcc=5, Vtt=(Vcc-2) , Voh=4.1 , Vol=3.3 , R=50 , Rs = 33 , 
then Rt = 119 ohms.

Check input common mode voltage:
Vcm(in)  = (Vcm_driver - Vtt)(R/(R+Rs)) + Vtt = 3.42 V., 
It's attenuated from the Vcm=3.7 at driver but it's still ok for 5V 
receiver.  In general, check Vcm(in) range for the receiver. 
Also, check swing at receiver:
Vih = (Voh - Vtt)(R/(R+Rs)) + Vtt = 3.66
Vil  = (Vol - Vtt)(R/(R+Rs)) + Vtt = 3.18
Vdiff = Vih - Vil = 480 mV
Vdiff,pk-pk  = Vin(1) - Vin(0) 
                =  ( Vih-Vil ) - ( Vil-Vih ) = 480 - (-480) = 960 mV
                =  2 * Vdiff

Resistor Rs must be placed next to driver.  If not, its purpose is 
defeated: to absorb back reflections from common mode (assuming 
perfect Zdiff match at load).  The closer to the load (R, Rt, and recvr 
pin) it's placed, the greater the mismatch to Zdiff and the more 
differential reflection occurs, as well.  That is, the diff. termination 
would look like 100 + 2*33 = 166, not 100.  

=========================
  ----- Original Message ----- 
  From: john lipsius 
  To: hariharan@xxxxxxxxxxx ; 'SI-LIST' 
  Sent: Saturday, February 15, 2003 3:54 PM
  Subject: Re: [SI-LIST] Re: PECL termination technique?


  Hariharan,

  The Cypress appnote (link below) does *NOT* match your original 
  email.  Your email doesn't show a ground tap and doesn't have the 
  220pF common mode filter.  

  I can only assume that your product works because the MC100's internal 
  pullups to 3.3v do the dc biasing for the Cypress drivers.  But, those 
  pullups are large, if they exist, so the driver dc current is small --- not 
  good.  They are near cutoff.  

  Also, lack of the common mode filter is just unwise.  It simply improves 
  your jitter or noise budget, which may be sufficient now, but only 
  marginally so.  Ie: it could fail if you change from the MC100 to another 
  device. 

  The appnote also relies on series R of 56ohm to damp the common mode, 
  and the R_odd that results is  (56+75)//82 = 50.4 ohms.  
  The drivers are dc loaded with 131 ohms, which is in range.  
  Very ingeniously, their termination uses just its own 5V supply to also 
  establish the normal 3.3V comm. mode at the load:  

  Vcm load     =  Vcm * 75 / (56 + 75)  
                   = (5-1.33) * 75 / (56 + 75) = 2.1 V

  In your design:
  Vcm load     =  3.67 * 60 / (33 + 60) = 2.3 V


  The Cy appnote shows this:

  -->>----------56---------------- 
            |            |
           82           75
            |            |
  Cypress  +5V-- 220pF --|--gnd     MC100 input
  driver    |            |                 
           82           75  
            |            |
  -->>---------56---------------- 



  I would just ask Cypress about using their scheme vs. yours with the 
  MC100 device.  

  See: 

  http://www.cypress.com/cfuploads/support/app_notes/sst33.pdf

    ----- Original Message ----- 
    From: hariharan 
    To: 'john lipsius' ; hariharan@xxxxxxxxxxx ; 'SI-LIST' 
    Sent: Saturday, February 15, 2003 2:51 AM
    Subject: [SI-LIST] Re: PECL termination technique?


    Hello John,

    Thanks for the mail. But the same termination seems have worked for the
    previous version of the present product. It has the same kind of PECL
    termination between CY7B951-SC (Cypress) to Motorolla's (MC100ELT23D).

    That's the reason I'm so curious how it would work?

    The present termination what I was describing looks like a standards LVDS
    (Differential) termination.

    Let me know if you have an answer.

    regards

    Hariharan

      -----Original Message-----
      From: john lipsius [mailto:johnlipsius@xxxxxxxxx]
      Sent: Friday, February 14, 2003 5:57 PM
      To: hariharan@xxxxxxxxxxx; SI-LIST
      Subject: Re: [SI-LIST] Re: PECL termination technique?


      Corrected eqns.  ... bad parentheses

      Ioh = [(Rt/R)*(Voh - Vol) + Voh] / ( R + 2Rt )
      Iol = [(Rt/R)*(Vol - Voh) + Vol] / ( R + 2Rt )

        ----- Original Message -----
        From: john lipsius
        To: hariharan@xxxxxxxxxxx ; SI-LIST
        Sent: Friday, February 14, 2003 4:21 AM
        Subject: [SI-LIST] Re: PECL termination technique?


        Hariharan,

        I agree something's missing.
        Perhaps your source outputs are pulled down close to the
        driver on another schematic sheet.  That's the only way it might
        work.  The MC100ELT23D may have internal input pulldowns, but
        that's just to assure safe input levels when undriven.

        Perhaps the termination was just 'borrowed' from another
        design and is missing the biasing.  The single diff. termination
        at the load is typical of long links, like a across a backplane, where
        grounds can be different.  The driver end would have the
        pulldowns for biasing in that case.

        The 33 and 120 ohm resistors appear to be series damping and
        Zdiff termination, but no biasing appears to be provided.

        Recap....
        1. Somewhere, these are required on each wire:
            * establish dc driver current for linear operation
            * bias to Vcm=Vcc-1.3  for example (typ. PECL)
        2. Another function is Zdiff matching at the load


        ---Rs-------------------
                  |
                  R
                  |
              Vtt ---Rt--gnd        Y termination with optional Rs
                  |                 for attenuation of reflections
                  R                 or for EMC
                  |
        ---Rs-------------------

        The Y termination can provide biasing & impedance matching
        by choosing R and Rt and setting Vtt=Vcc-2.  Then the drivers
        will operate near Vcm.
        Assuming Zdiff=100, then R=50 since Vtt is a 'virtual' gnd.
        Applying node current analysis, Voh+Vol = Vtt(2+[R/Rt]).
        Then R and Rt pop out.
        For Vcc=3.3V, Rt=R but for Vcc=5V,  Rt = 2.13*R , using typical PECL
        Voh, Vol.

        Tolerances:
        Just make sure you don't choose R and Rt such that, at VOLmin,
        a driver cuts off.   R should be 1% tol. or better.

        Ioh = (Rt/R)*(Voh - Vol) + Voh) / ( R + 2Rt )
        Iol = (Rt/R)*(Vol - Voh) + Vol) / ( R + 2Rt )

        Plugging in the Vol(min) and Voh(max) at worst case temperatures,
        Rt max., and Vcc(min) will give a min. Iol, which must be greater than
        some vendor minimum such as 0 mA (cutoff).  If one driver gets in cutoff
        it'll be slow and you'll develop a common mode in driven diff. signal
        which will skew your duty cycle, create comm mode reflections, worsen
        emc, etc.  The Rs helps attenuate the inevitable common mode noise
        even with a good termination.

        -John

          ----- Original Message -----
          From: hariharan
          To: si-list@xxxxxxxxxxxxx
          Sent: Thursday, February 13, 2003 8:51 PM
          Subject: [SI-LIST] PECL termination technique?


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          Blank
          Hi,

          This is regarding a PECL termination. I'm presently reviewing a
    hardware
          design, in that the designer has used a PECL to TTL converter for a
    clock
          Oscillator's PECL output connecting to a CPLD via a PECL to TTL
    translator.
          Here the designer has used a termination ie PECL - PECL
    (Differential), say
          he has used a 120 ohm RES connecting the positive and negative of the
          differnential pair.

                         (POS) +------33 ohms---------------------------+ (POS)
                                                                 >
                                                              120 ohms
                                                                 >
                        (NEG)   - ------33 ohms---------------------------- -
    (Neg)

          the devices are CY7B951-SC (Cypress)   to Motorolla's (MC100ELT23D).

          Here in the above case I understand the designer has opted for a power
          consumption less termination. But the usual termination we go in for
    is
          a Y termiantion ( with ref. to ONSEMI PECL design - Application note).


          Can anyone help me out to understand how the designer would have
    arrived at
          those values and the termination technique.

          regards
          Hariharan







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          <BODY background=3Dcid:328163704@14022003-0c2a=20
          style=3D"COLOR: #000000; FONT-FAMILY: Arial">
          <DIV>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003>Hi,</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN><SPAN =
          class=3D328163704-14022003>This=20
          is regarding a PECL termination. I'm presently reviewing a hardware =
          design, in=20
          that the designer has used a PECL to TTL converter for a clock =
          Oscillator's PECL=20
          output connecting to a CPLD via a PECL to TTL translator.
    </SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN><SPAN =
          class=3D328163704-14022003>Here=20
          the designer has used a termination ie PECL - PECL (Differential), say
    =
          he has=20
          used a 120 ohm RES connecting the positive and negative of the =
          differnential=20
          pair.</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
          p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;(POS)=20
          +------33 ohms---------------------------+ (POS)</SPAN></DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=

    p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=

    ;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=

    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=

    nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&gt;=20
          </SPAN></DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=

    p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=

    ;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=

    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
          nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;120=20
          ohms</SPAN></DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=

    p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=

    ;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=

    &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
          nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
          &gt;</SPAN></DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
          p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;(NEG)&nbsp;&nbsp;=20
          - ------33 ohms---------------------------- - (Neg)</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003>the devices are CY7B951-SC=20
          (Cypress)&nbsp;&nbsp; to Motorolla's (MC100ELT23D). </SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003>Here in the above case I =
          understand the=20
          designer has opted for a power consumption less termination. But the =
          usual=20
          termination we go in for is </SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003>a Y termiantion ( with ref. to =
          ONSEMI PECL=20
          design - Application note).</SPAN></DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
          p;&nbsp;=20
          </SPAN></DIV>
          <DIV>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003>Can anyone help me out to =
          understand how the=20
          designer would have arrived at those values and the termination=20
          technique.</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN class=3D328163704-14022003>regards</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003>Hariharan</SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN>&nbsp;</DIV>
          <DIV><SPAN=20

    class=3D328163704-14022003>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=

    p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=

    ;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
          &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=20
          </SPAN></DIV>
          <DIV><SPAN class=3D328163704-14022003></SPAN><BR>&nbsp;</DIV>
          <P>&nbsp;</P></BODY></HTML>

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