Hi Todd,
Thank you very much for your comments.
Actually, I am going to model the analyze the complete link with an EDA
tool and IBIS-AMI model to see how much timing margin I can get.
Regarding the PCIe compliance, from your email, it appears that you would
consider the combination of my custom PCIe card and Riser Card as an
Add-in-card. Am I right?
If we treat a custom PCIe cad + Riser Card as an Add-in-card (AIC), there
are some parameters that do not meet the AIC requirements.
For example, the AIC requires the data propagation delays does not exceed
750ps which is a trace length constraint.
The trace length on my custom PCIe card + Riser Card is longer than 750ps
and it may fail the AIC PCIe compliance.
Thanks,
Edin Bazo
On Mon, May 24, 2021 at 11:50 AM Westerhoff, Todd <
Todd_Westerhoff@xxxxxxxxxx> wrote:
Edin,
I think you've got that about right.
There are EDA tools that can analyze serial links for compliance with
applicable protocols, and some can handle the case you're describing, where
you're only designing part of the link and need a model supplied for the
rest. PCIe-3 is an end-end spec, so you need to model and analyze a
complete link.
If it were me, I'd start with PCIe-3 Compliance Analysis, since that's
fast, easy and predictable. I *might* run an IBIS-AMI simulation if I
thought the margins were tight, but since the design is an add-in card and
you don't know much about the motherboard other than the loss target, I'd
probably just stick with Compliance. IBIS-AMI models are meant to
represent specific components and equalization settings, and if you don't
know what the motherboard component will be - it's just conjecture.
Todd.
Todd Westerhoff
High-Speed Design Product Marketing | Electronic Board Systems (EBS)
Siemens EDA
300 Nickerson Rd, Marlboro, MA 01752
todd.westerhoff@xxxxxxxxxxx | office: 508-303-5821 | cell: 978-846-0203
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On
Behalf Of Edin Bazo
Sent: Sunday, May 23, 2021 12:44 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCIe simulation between an off-the-shelf motherboard
and custom PCIe card with custom riser card
Hi All,
I am going to design a custom PCIe gen3 card and a riser card for this
PCIe card.
The custom PCIe gen3 card (A) will be plugged into a custom riser card
(B) and then plug this riser card into a PCIe slot of an off-the-shelf
motherboard (M).
From what I understand, the budget of the insertion loss (IL) of PCIe is
22dB for Gen3, 6.5dB for a standard Add-in Card (AIC).
An off-the-shelf motherboard supports a standard AIC, so the worst-case
scenario IL for an off-the-shelf motherboard would be 15.5dB include PCB of
motherboard and CPU package, PCIe connector.
Am I understanding this correctly?
Since I don't have the motherboard model of an off-the-shelf motherboard,
I would need to create a model (S-parameter) of an off-the-shelf
motherboard for simulation with the custom PCIe card and custom riser card
that I am going to design.
There would be two options that I am considering as below:
1) Create an S-parameter for a motherboard with IL=15.5dB and simulate
with the custom PCIe card + custom riser card.
I need to make sure the IL of custom PCIe card + custom riser card <
6.5dB.
I'm considering this is a worst-case scenario and my custom PCIe card +
custom riser card should work with any motherboard in the market.
2) Create an S-parameter for the motherboard where the IL of the
motherboard + IL of my custom riser card = 15.5dB.
In this case, the IL of the motherboard will be less than 15.5dB and I
have to find an off-the-shelf motherboard that has IL <= 15.5dB - IL of my
custom riser card.
I think it is very difficult to find this motherboard since it is not easy
to get the IL of the motherboard from the vendor.
If you would simulate the above PCIe link, which option would make sense?
I appreciate your advice!
Thanks,
Edin Bazo
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