Hello,
if you use the clock official clock jitter tool you need to consider
that the standard download does not provide Templates for all required
configuration.
As far I remember for GEn3 @ 8Gb/s common clocked there are about 14
different configurations of CDR, peaking and ...(don't remember if there
was a third parameter..) but as mentioned before already only two
templates are supplied.
You need to pass ALL combinations that are described in the PCIe spec.
for Gen3 at 8Gb/s there is still common clocked and data clocked defined.
if you think about Gen4 at 8Gb/s there is only common clocked and
SRIS/SRNS. So far I have not checked the requirements for SRIS/SRNS.
So you need to know which RX architectures should be supported by your
clock.
But I expect the 14(?) combinations for CC RX Architecture are required
in any case.
Last but not least: also the scope vendor Compliance app implementation
allow to do Clock jitter tests.
If you have access to one of these it might be possible to use offline
generated traces.
Again: at least one of the scope vendors does not automatically test all
combinations, but you need to configure each of the 14(?) parameter
combinations manually and run the each test on it's own (or you script
the execution..) ..
Hermann
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Am 15.05.2018 um 18:03 schrieb Filip, Cristian:
Here is the link:One of the big clock buffer companies has one too. I don't remember where.
https://www.silabs.com/products/timing/pci-express-learning-center
You might want to check those documents as well:
https://www.silabs.com/documents/public/application-notes/AN562.pdf
https://www.silabs.com/documents/public/application-notes/an1104-making-accurate-clock-jitter-measurements.pdf
Thank you,
Cristian
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Wyatt Erickson
Sent: Tuesday, May 15, 2018 9:26 AM
To: hitheshn@xxxxxxxxx; SI-List
Subject: [SI-LIST] Re: PCIe gen3 Clock Jitter measurement
You need to use an external tool to process the clock data through a series
of different filters based on which compliance test you are running. You
basically capture a scope shot with a fast diff probe/scope. You save the
data and run it through a post processor. There are at least two compliance
test post-processors available. The original is from Intel here:
https://www.intel.com/content/www/us/en/design/technology/high-speed-io/tools.html
One of the big clock buffer companies has one too. I don't remember where.
These are the instruction I use for doing my measurements.
Step-by-step guide
Required Equipment:
Tektronix DSA7xxxx scope (8, 20 or 23GHz)
7xxxx series Compatible Differential Probe
PCI-SIG PCIe Clock Jitter Tool installed on a PC.
(S:\Applications\Intel\ClockJitterTool)
PCB to be tested (device under test or DUT)
Complete the Following Steps:
Connect the clock signal under test using a differential scope probe.
Set the voltage scale as to 50mV/div. Clipping is acceptable per Intel Issue
Set the time scale to 200us/div.
Set the sample rate to the maximum, must be greater than 12.5GS/s.
Set the scope to Run and verify the signal is present.
Set the scope to Single and capture a sample.
Navigate to File → Save As → Waveform. And save the capture.
Move the waveform file to a computer with the PCI-SIG PCIe Clock Jitter Tool
Open the PCIeclock Test tool.
Under “Waveform File” select browse and choose the file captured.
Set the File Type to Differential. Other fields can be left to default.
Select the the correct test from the Template File pull-down. See notes
below.
Click the Test File Button, A variety of windows with results will appear.
Using Alt-Print Screen to capture all windows associated with test template
including the clock jitter tool window and paste them into the SI document.
Repeat Steps 12 thru 14 for each appropriate template.
Typically we use these test profiles.
For PCIe Gen 2 devices run each PCIE_2_0_* template.
PCIE_2_0_5MHZ_1_5M_H3_FIRST
PCIE_2_0_5MHZ_1_5M_H3_STEP
PCIE_2_0_8MHZ_1_5M_H3_FIRST
PCIE_2_0_8MHZ_1_5M_H3_STEP
For PCIe Gen 3 devices run each PCIe Gen 2 Template and each PCIE_3_0_*
template
PCIE_3_0_2MHZ_4M_H3_FIRST
PCIE_3_0_2MHZ_5M_H3_FIRST
Hope that helps.
This tool can be used for all PCI Gen 2 and Gen 3 clocks.
Woohoo finally a question that I can answer...
Wyatt
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> On Behalf
Of Hithesh
Sent: Monday, May 14, 2018 5:14 PM
To: SI-List <si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] PCIe gen3 Clock Jitter measurement
EXTERNAL MAIL: si-list-bounce@xxxxxxxxxxxxx
Hi Experts,
I'm having some difficulty finding the specs for PCIe gen3 Common clock
jitter.
The spec is 1ps, but I can't find the freq range that its specified for.
For gen1,2 it was simple - 12KHz to 20MHz.
For Gen3, it looks like there are multiple frequency bands- 2-5MHz and
2-10MHz.
Also, how do you measure it. Do you use a Source signal analyzer or use the
compliance base board?
Any help is greatly appreciated.
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