Good question, I had a similar question years ago on DDR3 and DDR4 they have
single bit error correction. It was observed that some DIMS, that we were
monitoring had their correction circuits running all the time, tons of error
being corrected. I think you will find this is still a hot topic even today.
If we are looking to improve the system performance / watt then it make
sense to mitigate the engagement of the extra circuits. -Lyndell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Praveen Kumar
Sent: Monday, January 28, 2019 4:10 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCIe Gen3/Gen4 Presets optimization
Hi All,
Since PCIe Gen3/Gen4 does dynamic equalization what is the point of figuring
out optimum preset values ? (some For plug and play (involving System
Board/Addin_Card types of PCIe Devices) definitely it doesn't make sense
because users might introduce additional cables between RC & EP so different
scenarios need different presets but if the Root Complex and End points are
on same PCB is it required to figure out optimum preset values and override
(using SW) the preset values determined during dynamic equalization?
Note: I'm not saying Transmitter/Receiver Equalization Validation is not
needed.
Praveen
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