[SI-LIST] Re: PCIX Clock routing and connector
- From: <Robert_Washburn@xxxxxxxx>
- To: <for_si2003@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 17 Aug 2004 14:15:02 -0500
"1. The onboard Clock is routed 2.5" less than the ADD ON Card clock
length."
Assuming you mean the on-board clock is 2.5" longer than the add card.
"2. On scopeshot the onboard clock is lagging by about 160 ps than the
clock on the ADD ON Card."
Do the waveforms begin rising at roughly the same time? Are their slew
rates noticeably different? Input capacitance difference between two
receivers can contribute pretty significantly to skew differences (as
much as trace length differences on the order of 100s of mils).
"3. Though, it is still within limit ( PCIX Spec - 0.5 ns or 500ps), I
am wondering if I could do better to improve marging."
You can probably do better for the devices you're dealing with, but I'd
try to determine the source of the skew first. Namely, is the skew
difference input capacitance variation between receive devices or is it
strictly driver skew? If it's driver skew, you'd want to determine the
window of allowable skew at the output pins of the clock driver (based
on the synthesizer spec). If you plan to use more than one vendor, they
might not all have the same skew relationships of the PCI-X output pins.
If the clock driver is the source of the skew, you'd be optimizing the
board for that one vendor (or potentially that one part if it's not a
typical sample) while risking other vendors whose pins might be skewed
in reverse but still in-spec.
Before making any trace length adjustment, I'd find out where the
on-board device's input capacitance falls relative to the spec for it.
If you've got a particularly heavy or light add-in card in your test
environment, the skew you see could be very normal. Ditto if the skew
is driver related for one particular vendor.
robert
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of V S
Sent: Tuesday, August 17, 2004 1:49 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCIX Clock routing and connector
I am looking at the PCIX Clock skew between an onboard clock and a clock
on the ADD ON Card.=20
1. The onboard Clock is routed 2.5" less than the ADD ON Card clock
length.
2. On scopeshot the onboard clock is lagging by about 160 ps than the
clock on the ADD ON Card. Both measurements are taken under the Balls of
BGA.
3. Though, it is still within limit ( PCIX Spec - 0.5 ns or 500ps), I am
wondering if I could do better to improve marging.
4. It looks like the PCI connector and the cooresponding vias adds a
delay of the order 150 ps.
5. Under the light of above result, is it ok to route the system board
clk longer by 3.5" rather than 2.5"
than the clk going to PCI slot. Has anyone done that.
- Thanks
V. S.
=20
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