[SI-LIST] Re: PCI-X 1.0a simulation
- From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
- To: <Aubrey_Sparkman@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Dec 2005 10:44:29 -0800
Aubrey,
Point taken. But if I tweak the reference resistor and put it out of spec and
makes it work at 133MHz instead of the dead end 100MHz according to spec, I
have a product that has a competitive edge over someone just follow the spec
and ship a mediocre product. And if the driver is impedance controlled, how
much can it varies from lot to lot anyways ? Granted I have to set certain
conditions to make sure it is a production worthy system. We get paid to make
our company products competitive, not just glue things together and simulates
some junky IBIS models and scares ourselves to death because of the poor
quality reference models results that doesn't come close to reality.
Just my opinion also.
________________________________
From: si-list-bounce@xxxxxxxxxxxxx on behalf of Aubrey_Sparkman@xxxxxxxx
Sent: Thu 12/29/2005 9:13 AM
To: Chris Cheng
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCI-X 1.0a simulation
Chris,=20
Isn't the logical extension of your "Forget about ... any model"
comment, Forget about simulation? I think this underscores that we
should explore **ONLY** the solution space defined by the spec. After
all, we can't simulate every possible case where an IC supplier might
choose to go outside the spec.
But that's just my opinion.... :-)
Aubrey Sparkman=20
Enterprise Engineering Signal Integrity Team
Dell, Inc.=20
Aubrey_Sparkman@xxxxxxxx=20
(512) 723-3592
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Wednesday, December 28, 2005 2:42 PM
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCI-X 1.0a simulation
Forget about IBIS model or any model. I have come across at least two =
=3D
PCIX bridges that has undocumented impedance control. How on earth a =3D
single IBIS or even SPICE model can describe it when you can change the
=3D reference resistor to affect the drive strength ? I can tweak the =
=3D
reference resistor to make it work from 100MHz to 133MHz with =3D
multi-loads but I have no way of simulating it.
To make it more fun, some brilliant I/O designer decided to update his =
=3D
drive strength while the driver is active. Makes it fun to design those
=3D weak pull ups.=3D20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Wednesday, December 28, 2005 8:34 AM
To: christopher.mcgrath@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCI-X 1.0a simulation
Chris
I'm in agreement with you. PCI-X is a reflected wave bus, which makes it
=3D
extremely sensitive to bus length, loading, SSO and other package=3D20
effects. PCI-X busses that I have seen were designed into low cost=3D20
packages that had extreme issues with power delivery and signal=3D20
crosstalk. In some, where the drivers had fast edges and low =
output=3D20
impedance, reflected reverse crosstalk generated in the package=3D20
dominated performance. In fact, in some cases it was not possible =
to=3D20
design PCB traces that had worse crosstalk than the package. In
other=3D20 cases, "PCI-X receivers" did not meet the voltage tolerance
required by=3D20 the specification, causing us to use vast numbers of
series attenuators=3D20 to keep overshoot from blowing up the receivers.
In yet others, FET=3D20 switch packages used for hot-swaping, generated
more signal-to-signal=3D20 crosstalk than any other component or trace.
I'm generally not comfortable with running PCI-X at bus rates above
66=3D20 MHz, without some significant spice modeling of drivers, =
receivers
and=3D20 packages. Many 100 MHz busses that I've looked at are =
marginal,
with=3D20
133 MHz being a pipedream =
(http://en.wikipedia.org/wiki/Pipe_dream),=3D20
except for short point-to-point interconnect.
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed=3DAE is the registered service mark of Teraspeed Consulting
Group LLC
Mcgrath, Christopher wrote:
>Having done a significant amount of PCI-X 1.0 simulations in my last=20
>life, I concur with all of the comments so far. There is a tremendous=20
>difference between driver models for various ASICs even if they are all
>consistent with the PCI-X specification. I also found that not having=20
>=3D
a
>package model (or at least an approximation to start out with) can=20
>severely skew the results to the point that simulating without them is=20
>pretty much a waste of time.
>
>We had to "make do" with an IBIS model from a vendor and they took a=20
>while to get us a version with the package data incorporated into it, =
=3D
so
>we did some analysis without it. When we finally got the full model, =
=3D
we
>saw that we had less margin on timing but significantly less transient=20
>overshoot/undershoot. =3D3D20
>
>-Chris
>
>
> =3D20
>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>> =3D20
>>
>[mailto:si-list-bounce@xxxxxxxxxxxxx] On =3D20
>
>>Behalf Of Aubrey_Sparkman@xxxxxxxx
>>Sent: Tuesday, December 27, 2005 4:02 PM
>>To: weirsi@xxxxxxxxxx; naren.thesia@xxxxxxxxx
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: PCI-X 1.0a simulation
>>
>>Naren,
>>Please take another look at the specs. There are several important=20
>>differences between the PCI spec and the PCI-X spec so I would =3D
strongly
>>discourage using a generic PCI model for a PCI-X driver.
>>
>>You can make a buffer model that covers the max and min conditions =3D
from
>>the spec. Can you get the package models for your ASIC to use with =
=3D
the
>>buffer model?
>>
>>Most GOOD system houses have faced conditions like this. You start
>> =3D20
>>
>with
> =3D20
>
>>the appropriate (PCI VS PCI-X) "spec based" model until your ASIC=20
>>supplier gets their silicon finished and their model working and=20
>>correlated. Then you continue to use your "spec based" models to test
>>for the range of things that can be plugged into your slots.
>>
>>Good luck,
>>Aubrey Sparkman
>>Enterprise Engineering Signal Integrity Team Dell, Inc.
>>Aubrey_Sparkman@xxxxxxxx
>>(512) 723-3592
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>> =3D20
>>
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
> =3D20
>
>>On Behalf Of steve weir
>>Sent: Tuesday, December 27, 2005 6:53 AM
>>To: Naren Thesia
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: PCI-X 1.0a simulation
>>
>>Naren, I am sorry, but I don't see anything here to change my =3D
opinion.
>>Steve
>>At 04:54 PM 12/27/2005 +0530, Naren Thesia wrote:
>> =3D20
>>
>>>But my ASIC is in development stage.
>>>For IBIS mainly two things
>>> * Pin & package parasitics
>>> * VI characteristics of buffer.
>>>I have package/pin parasitics of ASIC(Driver).
>>>Now I want to take VI characteristics from other device model.
>>>The reason behind I am assuming is that PCI output will be standard =
=3D
as
>>>PCI specifications.
>>>
>>>Please let me know about your opinion....
>>>
>>>
>>>
>>>
>>>On 12/27/05, steve weir <<mailto:weirsi@xxxxxxxxxx>weirsi@xxxxxxxxxx>
>>> =3D20
>>>
>>wrote:
>> =3D20
>>
>>>I wouldn't do that. Get the driver model.
>>>
>>>Steve.
>>>At 04:22 PM 12/27/2005 +0530, Naren Thesia wrote:
>>> =3D20
>>>
>>>>Hi all,
>>>>
>>>>In my circuit there are two devices PCI-X 1.0a driver and receiver.
>>>>I have IBIS model for receiver.
>>>>I don't have IBIS model for driver.
>>>>
>>>>Can I use any generic PCI model for my driver?
>>>>Anyone has faced condition like this?
>>>>
>>>>Thanks in Advance.....
>>>>
>>>>--
>>>>Regards
>>>>Naren
>>>>
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